“…Further, cache energy saving can also be achieved using circuit-level techniques (e.g., lowleakage devices), however, in this paper we mainly focus on architecture-level techniques which allow runtime cache power management. Lastly, since different techniques have been evaluated using different simulation infrastructure and workloads, we do not include their quantitative improvement [9], [15], [16], [18], [18], [45]- [48] ESTs utilizing hardware support [12], [13], [48]- [53] ESTs utilizing software support [17], [23]- [26], [38], [54]- [56] ESTs utilizing compiler support [40], [41], [45], [57], [58] results. Rather, we focus on their key design principles, which can provide valuable insights.…”