It has been noticed that for ultrashallow ion implanted dopant profiles, the metallurgical junction is not at the same location as the peak of the spreading resistance profile, i.e., the on-bevel junction. This can be attributed to the carrier redistribution effect. Furthermore, the pressure under the spreading resistance probes causes band-gap narrowing of the material under the probes. This pressure-induced band-gap narrowing effect increases the intrinsic carrier concentration of the semiconductor material. An inverse algorithm used to convert spreading resistance profiles into the electrically active dopant profiles, taking both carrier redistribution and band-gap narrowing into account, is presented in this article. Using this algorithm, the depth of the metallurgical junction of a shallow ion implanted p ϩ n profile is determined to be 0.121 m from the surface, whereas the on-bevel junction depth is 0.089 m. The recovered dopant concentration profile agrees very well with that obtained from secondary ion mass sepctrometry. The algorithm is shown to work very well also for an n ϩ p junction.
Highly sensitive, accurate and precise methods for measuring the properties of dielectrics used in sub 0.13 jam technology are required. It is particularly critical to monitor the electrical properties of the gate dielectric. The electrical properties of thin dielectrics are assessed with a new, non-contaminating, non-damaging elastic probe. This probe forms a small diameter (-30 um to 50 um) Elastic Metal gate (EM-gate) on the surface of a dielectric. Subsequent electrical measurements are made with advanced Capacitance-Voltage (CV), Conductance-Voltage (GV), and Current-Voltage (IV) techniques. Valuable and essential information about the dielectric thickness and quality, leakage current, Si-SiO 2 interface quality, and channel carrier density profile is obtained.
Articles you may be interested inCoulomb scattering in high-κ gate stack silicon-on-insulator metal-oxide-semiconductor field effect transistors J. Appl. Phys.Evidence for mobility enhancement in double-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors Unique method to electrically characterize a single stacking fault in silicon-on-insulator metal-oxide-semiconductor field-effect transistors This article explores electrical characterization methods for silicon-on-insulator ͑SOI͒ structures with a nondamaging elastic metal gate ͑EM gate͒. Important material electrical properties related to the top silicon layer, gate dielectric and interfaces, and buried oxide are addressed. The techniques utilized are currently under development for SOI and are based on EM-gate capacitance-voltage methods, current-voltage methods, and a back channel metal-oxide-semiconductor transistor that utilizes elastic probes to form a temporary source and drain.
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