Electrical characterization of silicon-on-insulator structures with a nondamaging elastic–metal gate

Abstract

Articles you may be interested inCoulomb scattering in high-κ gate stack silicon-on-insulator metal-oxide-semiconductor field effect transistors J. Appl. Phys.Evidence for mobility enhancement in double-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors Unique method to electrically characterize a single stacking fault in silicon-on-insulator metal-oxide-semiconductor field-effect transistors This article explores electrical characterization methods for silicon-on-insulator ͑SOI͒ structures with a nondamaging elastic metal gate ͑EM gate͒. Important material electrical properties related to the top silicon layer, gate dielectric and interfaces, and buried oxide are addressed. The techniques utilized are currently under development for SOI and are based on EM-gate capacitance-voltage methods, current-voltage methods, and a back channel metal-oxide-semiconductor transistor that utilizes elastic probes to form a temporary source and drain.