Single-walled carbon nanotubes (CNTs) may enable the fabrication of integrated circuits smaller than 10 nanometers, but this would require scalable production of dense and electronically pure semiconducting nanotube arrays on wafers. We developed a multiple dispersion and sorting process that resulted in extremely high semiconducting purity and a dimension-limited self-alignment (DLSA) procedure for preparing well-aligned CNT arrays (within alignment of 9 degrees) with a tunable density of 100 to 200 CNTs per micrometer on a 10-centimeter silicon wafer. Top-gate field-effect transistors (FETs) fabricated on the CNT array show better performance than that of commercial silicon metal oxide–semiconductor FETs with similar gate length, in particular an on-state current of 1.3 milliamperes per micrometer and a recorded transconductance of 0.9 millisiemens per micrometer for a power supply of 1 volt, while maintaining a low room-temperature subthreshold swing of <90 millivolts per decade using an ionic-liquid gate. Batch-fabricated top-gate five-stage ring oscillators exhibited a highest maximum oscillating frequency of >8 gigahertz.

An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.

Carbon nanotube (CNT)-based electronics are a potential candidate to replace silicon complementary metal-oxide-semiconductor (CMOS) technology, which will soon meet its performance limit at the 7 or 5 nm technology node 1,2 . Prototype device studies using individual CNTs have shown that nanotube electronics have the potential to outperform Si CMOS technology in both performance and power consumption [3][4][5][6] , and are even close to the theoretical limits for all field-effect-transistor(FET)-based binary switches 7,8 . Recently, FETs were fabricated using aligned CNT arrays, and shown to have a higher channel conductance (at a lower bias) than that of Si CMOS FETs 9 . However, the key performance metrics reported for such CNT FETs, including on-state current density (I on ) and transconductance (g m ), are still substantially lower than those of conventional Si CMOS FETs at the same characteristic length [9][10][11][12][13] . The ideal material system for high-performance CNT electronics has been identified as a parallel array film of intrinsic pure semiconductor single-walled nanotubes of a single chirality with a diameter of approximately 1.3 nm and no defects, and a tube-tube spacing of 5-8 nm (ref. 14 ). Although such an ideal material system is yet to be realized, many breakthroughs in the purification and controlled synthesis of CNTs have been made in recent years [15][16][17][18][19] , suggesting the possibility of achieving the required nanotube purity and array density before 2020 14 . Using randomly oriented or aligned CNT array films, various types of CNT thin-film FETs have been fabricated [9][10][11][12][13] . However, hindered by the limited performance of nanotube FETs, the operation speed of CNT integrated circuits (ICs) 20-31 typically falls short of their expected terahertz potential, and that achieved by Si CMOS circuits (gigahertz), by several orders of magnitude. Notably, CNT-based ring oscillators (ROs) with an oscillation frequency (f o ) of 282 MHz have recently been reported 32 . However, CNT-thin-film-based ICs typically have a working frequency of less than 1 MHz, which might be useful for flexible electronics, but is not suitable for mainstream high-performance CMOS technology 33 . In this study, we used a randomly oriented CNT film to build CNT FETs and ICs, fabricating, in particular, five-stage ROs with f o of up to 5.54 GHz. The random CNT film is essentially the same as a network film, but here we used the term 'random film' to emphasize that our FETs are contact dominated and have a different transport mechanism to that of junction-dominated network-type FETs 34,35 . In principle, aligned CNT arrays would provide better device performance, but it remains a challenge to obtain wafer-scale aligned CNT arrays with high uniformity, high density and high semiconductor purity for constructing high-performance ICs. Although it is not the ideal scheme, the FET-and IC-based random CNT film can nevertheless provide a feasible demonstration to assess the floor-level performance (f...

No abstract

high carrier mobility, and good air stability, it has the possibility to serve as the channel material of postsilicon era. Disappointingly, most existing 2D semiconductors cannot meet these requirements simultaneously, including the most concerned 2D MoS 2 and black phosphorene (BP). [8][9][10][11][12] Experimentally, 2D MoS 2 FETs have been scaled down to the sub-10 nm region, [13][14][15] but the low on-current (<250 µA µm −1 ) mainly caused by the low carrier mobility fails to meet the International Technology Roadmap for Semiconductors (ITRS) requirements, [16] which is in accord with the results of the ab initio quantum transport simulations. [17] 2D BP FETs own high carrier mobility but are so sensitive to the air that their device performance degenerates when exposed under ambient condition. [18,19] Therefore, it is crucial to find a 2D channel material with a modest band gap, large drive current, and high air stability to continue Moore's law.Tellurium (Te), a p-type semiconductor, consists of individual helical Te chains that are stacked together by van der Waals force. [20] Recently, atomically thin tellurene (2D form of Tellurium) has been fabricated by a substrate-free solution process and molecular beam epitaxy on a graphene/6H-SiC substrate, respectively. [21][22][23] 2D tellurene possesses an anisotropic structure and is constituted of alternate tetragonal and hexagonal rings. [24,25] The band gap of tellurene monotonically decreasesThe merging 2D semiconductor tellurene (2D Group-VI tellurium) is a possible channel candidate for post-silicon field-effect transistor (FETs) due to its high carrier mobility, high drive current, and excellent air stability. The performance limits of sub-5-nm ML tellurene metal-oxide-semiconductor FETs (MOSFETs) are explored by employing exact ab initio quantum transport simulations. An optimized p-type ML tellurene MOSFET meets both the high performance (along both the armchair and the zigzag directions) and the low power (along the armchair direction) requirements of the International Technology Roadmap for Semiconductors (ITRS) at a gate length of 4 nm with a negative capacity dielectric. Hence, choosing ML tellurene as the channel material provides a novel route to continue the Moore's law to 4 nm.

Inspired by the recent achievements of the two-dimensional (2D) sub-5 nm MoS 2 field effect transistors (FETs), we use the ab initio quantum-transport methods to simulate the transport properties of the sub-5 nm gate-length monolayer (ML) MoS 2 MOSFETs. We find that the ML MoS 2 double-gated MOSFETs (DGFETs) with the 1, 3, and 5 nm gate length fail to meet the on-state current requirements in the International Technology Roadmap for Semiconductors (ITRS) for high-performance (HP) devices. However, both the ML MoS 2 n-and p-DGFETs with 5 nm gate length can address the requirements in the ITRS for low-power (LP) applications in terms of on-state current, effective delay time, and power-delay products (PDPs). After the introduction of the negative capacitance dielectric layer, the ML MoS 2 p-DGFETs can satisfy the LP application requirements of ITRS until the gate length scales down to 3 nm. Hence, ML MoS 2 remains a potential channel candidate for LP applications in the sub-5 nm scale.

No abstract

No abstract