Sub-5 nm Monolayer MoS₂ Transistors toward Low-Power Devices

Abstract

Inspired by the recent achievements of the two-dimensional (2D) sub-5 nm MoS 2 field effect transistors (FETs), we use the ab initio quantum-transport methods to simulate the transport properties of the sub-5 nm gate-length monolayer (ML) MoS 2 MOSFETs. We find that the ML MoS 2 double-gated MOSFETs (DGFETs) with the 1, 3, and 5 nm gate length fail to meet the on-state current requirements in the International Technology Roadmap for Semiconductors (ITRS) for high-performance (HP) devices. However, both the ML MoS 2 n-and p-DGFETs with 5 nm gate length can address the requirements in the ITRS for low-power (LP) applications in terms of on-state current, effective delay time, and power-delay products (PDPs). After the introduction of the negative capacitance dielectric layer, the ML MoS 2 p-DGFETs can satisfy the LP application requirements of ITRS until the gate length scales down to 3 nm. Hence, ML MoS 2 remains a potential channel candidate for LP applications in the sub-5 nm scale.

Giant Photoluminescence Enhancement and Carrier Dynamics in MoS2 Bilayers with Anomalous Interlayer Coupling

“…Transition metal dichalcogenides (TMDCs) have been widely viewed as promising candidates in the next generation of nanophotonics [ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 ], electronics [ 10 , 11 , 12 , 13 , 14 , 15 ] and valleytronics [ 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 ] due to their unique optical properties and spin-valley configurations. As characterized by interlayer van der Waal forces [ 24 ], optical properties of two-dimensional TMDCs are dominated by excitons and vary significantly with their layer index.…”

Device performance and strain effect of sub-5 nm monolayer InP transistors

“…The optimal I on of the ML silicane and MoS 2 MOSFETs at L g = 1, 3, and 5 nm are also shown for comparison. 41,42 For the ML InP HP transistors, I on enhances with increasing the gate length without UL, and only I on at L g = 5 nm exceeds the ITRS standards. After adding UL, I on could still reach the ITRS standards until L g is decreased to 2 nm.…”

“…The better HP performance of the ML InP MOSFETs is probably associated with the smaller electron m * of the ML InP (0.093 m e ) than the ML MoS 2 (0.45 m e ) and silicane (0.161 m e ). 41,42…”

“…5(a) and (b) show the optimal τ of the n -type 2D ML material (InP, silicane, MoS 2 , Bi 2 O 2 Se, InSe, and arsenene) HP and LP MOSFETs, respectively. 41–46 The detailed τ of the ML InP MOSFETs are displayed in Tables 1 and 2. For the HP devices, τ of the ML InP MOSFETs can reach the ITRS demands for all the gate lengths.…”

“…5(c) and (d) display the optimal PDP of the 2D ML material (InP, silicane, MoS 2 , Bi 2 O 2 Se, InSe, and arsenene) HP and LP MOSFETs, respectively. 41–46 When L g is decreased to 1 nm, both the ML InP HP and LP MOSFETs fulfill the ITRS demands. For both the HP and LP applications, nearly all PDPs of the ML MoS 2 and Bi 2 O 2 Se MOSFETs exceed the ML InP MOSFET counterparts, indicating a poorer device performance than the ML InP MOSFETs.…”