The increase of integrated circuits performances requires ultra-low dielectric constant (ULK) materials to minimize the drawbacks of miniaturization. Amorphous SiOCH are promising candidates for ULK materials as porosity can be introduced via a two steps elaboration. In a first step, organo-silicon species and organic species are co-deposited by PECVD. Then, a thermal annealing, alone or assisted by UV radiation, removes the organic labile phase and creates pore inclusions into the final material. In this work, the extendibility of this porogen approach is investigated in order to lower the dielectric constant. An increase of the porogen loading in hybrid film is studied by tuning the precursors ratio injected in the plasma gas feed. The increase of organic species amount is operated in order to create more pores sites. However, the post-treatment does not lead automatically to higher porosity. Actually, an increase of the porosity is observed only until a porogen loading limit and decreases above this limit. The shrinkage of the film during the post-treatment can explain this limitation. For high ratios of porogen, the film shrinkage increases drastically and leads to a decrease of the porosity finally created. At last, the link between porosity and dielectric constant is enlightened and a minimum in term of K value is reached with both post-treatments: dielectric constant of 2.1 and 2.3 are obtained using respectively thermal treatment and UV curing.
A roadmap extending far beyond the current 22nm CMOS node has been presented several times.[1] This roadmap includes the use of a highly regular layout style which can be decomposed into "lines and cuts."[2] The "lines" can be done with existing optical immersion lithography and pitch division with self-aligned spacers.[3] The "cuts" can be done with either multiple exposures using immersion lithography, or a hybrid solution using either EUV or direct-write ebeam.[4] The choice for "cuts" will be driven by the availability of cost-effective, manufacturing-ready equipment and infrastructure.Optical lithography improvements have enabled scaling far beyond what was expected; for example, soft x-rays (aka EUV) were in the semiconductor roadmap as early as 1994 since optical resolution was not expected for sub-100nm features. However, steady improvements and innovations such as Excimer laser sources and immersion photolithography have allowed some manufacturers to build 22nm CMOS SOCs with single-exposure optical lithography.With the transition from random complex 2D shapes to regular 1D-patterns at 28nm, the "lines and cuts" approach can extend CMOS logic to at least the 7nm node. The spacer double patterning for lines and optical cuts patterning is expected to be used down to the 14nm node. In this study, we extend the scaling to 18nm half-pitch which is approximately the 10-11nm node using spacer pitch division and complementary e-beam lithography.For practical reasons, E-Beam lithography is used as well to expose the "mandrel" patterns that support the spacers. However, in a production mode, it might be cost effective to replace this step by a standard 193nm exposure and applying the spacer technique twice to divide the pitch by 3 or 4.The Metal-1 "cut" pattern is designed for a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Since the final conductor is defined by a Damascene process, the "cut" patterns become islands of resist blocking hard-mask trenches. The shapes are often small and positioned on a dense grid making this layer to be the most critical one. This is why direct-write e-beam patterning, possibly using massively parallel beams, is well suited for this task. In this study, we show that a conventional shaped beam system can already pattern the 11nm node Metal-1 layer with reasonable overlay margin.The combination of design style, optical lithography plus pitch-division, and e-beam lithography appears to provide a scaling path far into the future.
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