Materials Research Society Symposium Proceedings 2008
DOI: 10.1557/proc-1112-e03-03
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The Effect of Process Parameters on Electrical Properties of High Density Through-Si Vias

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Cited by 3 publications
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“…Other strategies are being explored to pursue device miniaturization. Among them, a promising approach consists in stacking several chips on top of each other to increase the complexity of the device without compromising its compactness [113][114][115]. In this architecture, a major challenge is the deposition of thin and continuous metallic layers in Through Silicon Vias (TSVs), the vertical holes interconnecting neighbouring levels.…”
Section: Further and Future Applicationsmentioning
confidence: 99%
“…Other strategies are being explored to pursue device miniaturization. Among them, a promising approach consists in stacking several chips on top of each other to increase the complexity of the device without compromising its compactness [113][114][115]. In this architecture, a major challenge is the deposition of thin and continuous metallic layers in Through Silicon Vias (TSVs), the vertical holes interconnecting neighbouring levels.…”
Section: Further and Future Applicationsmentioning
confidence: 99%
“…The technology is based on a stack of two silicon wafers using Direct Bonding technology [12]. A 200 mm wafer with one Cu damascene level (M BOT ) is bonded face down on a Si bulk carrier using SiO 2 bonding, and thinned down to 15 µm.…”
Section: Technologymentioning
confidence: 99%