We demonstrate the impact of atomic-layer-deposited TiN gate on the characteristics of W/TiN/SiO2/p-Si metal–oxide–semiconductor (MOS) systems. Damage-free gate oxide quality was attained with atomic-layer-deposition (ALD)–TiN as manifested by an excellent interface trap density (Dit) as low as ∼4×1010 eV−1 cm−2 near the Si midgap. ALD–TiN improved the Dit level of MOS systems on both thin SiO2 and high-permittivity (high-k) gate dielectrics. The leakage current of a MOS capacitor gated with ALD–TiN is remarkably lower than that with sputter-deposited TiN and poly-Si gate at the similar capacitance equivalent thickness (CET). Less chlorine content in ALD–TiN films appears to be pivotal in minimizing the CET increase against postmetal anneal and improving gate oxide reliability, paving a way for the direct metal gate process.
We report interface and dielectric reliability characteristics of n+ polycrystalline-silicon (poly-Si)/Al2O3/Si metal–oxide–semiconductor (MOS) capacitors. Al2O3 films were prepared by atomic layer chemical vapor deposition using Al(CH3)3 and H2O vapor. Interface state density (Dit) and dielectric reliability properties of n+ poly-Si/Al2O3/Si MOS structures were examined by capacitance–voltage, conductance, current–voltage, and time-dependent dielectric breakdown measurements. The Dit of the n+ poly-Si/Al2O3/Si MOS system near the Si midgap is approximately 8×1010 eV−1 cm−2 as determined by the conductance method. Frequency dispersion as small as ∼20 mV and hysteresis of ∼15 mV were attained under the electric field of ±8 MV/cm. The gate leakage current of ∼36 Å effective thickness Al2O3 dielectric measured at the gate voltage of −2.5 V is ∼−5 nA/cm2, which is approximately three orders of magnitude lower than that of a controlled oxide (SiO2). Time-dependent dielectric breakdown data of Al2O3/Si MOS capacitors under the constant current/voltage stress reveal excellent charge-to-breakdown characteristics over controlled oxide. Reliable gate oxide integrity of Al2O3 gate dielectric is manifested by the excellent distribution of gate oxide breakdown voltage on 128 million MOS capacitors having isolation edges. Extracted time constant and capture cross section of the Al2O3/Si junction are discussed.
Quadratic voltage coefficient of capacitance ͑VCC͒ for ZrO 2-SiO 2 multilayered dielectric metal-insulator-metal capacitors depends strongly on the stacking sequence of the layered dielectrics. The quadratic VCC of an optimized SiO 2 / ZrO 2 / SiO 2 stack and ZrO 2 / SiO 2 / ZrO 2 stack were +42 and −1094 ppm/ V 2 , respectively, despite the same total SiO 2 and ZrO 2 dielectric thickness in the stack. The observed difference in quadratic VCC depending on dielectric stacking sequence is explained by taking into account both the interface and bulk dielectric responses to the applied voltage.
This paper presents for the first time a full 32nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (A VT ) improvement (A VT~2 .8mV.um) and low 1/f noise aligned with poly SiON are reported. Excellent Static Noise Margin (SNM) of 213mV has been achieved at low voltage for a high density 0.157um 2 SRAM cell. Hierarchical BEOL based on Extreme Low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125ºC.
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