In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1).This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm 2 , providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results.Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.
Microelectronics industry leaders routinely name mask technology and mask supply issues of cost and cycle time as top issues of concern. A survey was initiated in 2002 with support from International SEMATECH (ISMT) and administered by SEMI North America to gather information about the mask industry as an objective assessment of its overall condition. 1 This paper presents the results of the second annual survey which is an enhanced version of the inaugural survey building upon its strengths and improving the weak points. The original survey was designed with the input of member company mask technologists, merchant mask suppliers, and industry equipment makers. The assessment is intended to be used as a baseline for the mask industry and the microelectronics industry to gain a perspective on the technical and business status of the critical mask industry. An objective is to create a valuable reference to identify strengths and opportunities and to guide investments on critical-path issues. As subsequent years are added, historical profiles can also be created. This assessment includes inputs from ten major global merchant and captive mask manufacturers representing approximately 80% of the global mask market (using revenue as the measure) and making this the most comprehensive mask industry survey ever. The participating companies are: Compugraphics, Dai Nippon Printing, Dupont Photomask, Hoya, IBM, Infineon, Intel, Taiwan Mask Company, Toppan, and TSMC.Questions are grouped into five categories: General Business Profile Information; Data Processing; Yields and Yield loss Mechanisms; Delivery Time; and Returns and Services. Within each category are a multitude of questions that create a detailed profile of both the business and technical status of the mask industry.
The International Venture for Nanolithography (INVENT) initiative announced in mid 2005, a unique industryuniversity consortium between the College of Nanoscale Science and Engineering at Albany and a group of leading edge integrated device manufacturers, has launched an extensive R&D program on EUV lithography (EUVL). The overall scope of the INVENT EUVL program, the status of our efforts to establish a baseline lithography process on a full-field EUVL scanner, and our progress in evaluating EUV resist materials, in designing a custom reticle for scanner characterization and in developing an actinic EUV mask imaging microscope, are discussed.
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