The use of EUV lithography to produce demonstration devices

Abstract

In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1).This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm 2 , providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results.Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.

Evaluation of EUV resist materials for use at the 32 nm half-pitch node

“…Currently available materials have performance sufficient for 45nm 4 and 32nm 5 logic ground-rule full-field demonstrations. Resist improvements for more demanding 32nm and 22nm development, which requires increasingly refined flare and shadowing compensation as well as OPC methodology, are gaining importance.…”

EUV patterning successes and frontiers

“…Though development of photoresists for EUV has been taking place for over a decade [1,2], much less has been explored regarding integration of EUV lithography into the whole patterning process [3], to the point of actually yielding semiconductor devices at a feature scaling that is advantageous over 193 immersion multi-patterning schemes. Indeed, now in the last 1-2 years, there has been major advancement in the integration and yield demonstration of EUV patterning as a replacement for >40nm pitch litho-etch-litho-etch BEOL metal patterning [4], as well as <40nm pitch BEOL metal patterning [5].…”

Evaluating scatterometry 3D capabilities for EUV

“…As extreme ultraviolet lithography (EUVL) [1,2] is more widely adopted to fabricate smaller and smaller patterns for electronic devices, scatterometry faces new challenges due to several reasons. For 14nm node and beyond, the feature size is nearly an order of magnitude smaller than the shortest wavelength used in scatterometry.…”