In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1).This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm 2 , providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results.Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.
A plasma produced by laser irradiation of solid targets is a promising candidate as an efficient x-ray lithography source. In order to design a practical laser created x-ray source, it is necessary to study the factors affecting the x-ray emission. For this purpose, we investigate both theoretically and experimentally the influence of the laser target parameters on the x-ray emission in different spectral ranges for two laser wavelengths (λ=1.06 μm, λ=0.26 μm). From these results and considering mask transmission, resist sensitivities, and wafer throughput, we establish the characteristics of the laser required as an x-ray lithography source with performance acceptable for industrial applications.
In this paper, results and analysis are presented from Advanced Micro Devices' (AMD) efforts at calculating lithography dose and focus parameters using scatterometry metrology and semi-physical CD models. The system takes advantage of the accurate and precise top and bottom CD data produced by scatterometry to differentiate dose and focus variation. To build the lithography process model, scatterometry data is generated for each field of a focus-exposure matrix (FEM) wafer, and the resulting top and bottom CD data is used to fit the parameters of series expansions relating CD to dose and focus. When new CD data is generated, the models can be inverted to solve for dose and focus independently. Our methodology employs a flexible modeling and inversion approach in an attempt to make the technique applicable to any production film stack and any line spacing regime. The quality of the inversion results are highly correlated to the degree of focus observability present in the system. Our results will show how a series of litho process with varied film stacks and line/space ratios respond to this technique, and we will report some best practices for a variety of use cases ranging from equipment characterization to focus monitoring on product.
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