Abstract-Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, 3-D integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Among others, thermomechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effects of thermally induced stresses on the interfacial reliability of TSV structures. First, 3-D distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semianalytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results from finite element analysis (FEA). The stress analysis suggests interfacial delamination as a potential failure mechanism for the TSV structure. An analytical solution is then obtained for the steady-state energy release rate as the upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. With these results, the effects of the TSV dimensions (e.g., via diameter and wafer thickness) on the interfacial reliability are elucidated. Furthermore, the effects of via material properties and dielectric buffer layers are discussed.
A kinetic analysis was formulated for electromigration enhanced intermetallic evolution of a Cu-Sn diffusion couple in the Sn-based Pb-free solder joints with Cu under bump metallurgy. The simulated diffusion couple comprised the two terminal phases, Cu and Sn, as well as the two intermetallic phases, Cu 3 Sn and Cu 6 Sn 5 , formed between them. The diffusion and electromigration parameters were obtained by solving the inverse problem of the electromigration enhanced intermetallic growth, and they were compatible with the literature values. Finite difference method was applied to the whole simulated domain to solve for the mass transport kinetics within the intermetallic phases and across each interface of interest. Simulation showed that, when electromigration effect was absent ͑zero current͒, intermetallic growth followed a parabolic law, suggesting a diffusion controlled mechanism for thermal aging. However, under significant current stressing ͑4 ϫ 10 4 A/cm 2 ͒, the growth of the dominant intermetallic Cu 6 Sn 5 clearly followed a linear law, suggesting a reaction controlled mechanism for electromigration. Simulation results were consistent with the experimental observations. The analysis of vacancy transport was also incorporated with the model, and the results showed substantial increase in vacancy concentration at the Cu 6 Sn 5 phase near the Cu 3 Sn/ Cu 6 Sn 5 interface. The peaking of the vacancy concentration explains the substantial Kirkendall void formation under electromigration at this region.
Abstract-Three-dimensional (3-D) integration with throughsilicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in the TSV structures can affect the device performance by degrading carrier mobility and raise serious reliability concerns. In this paper, the effect of thermal stresses in TSV structures on carrier mobility and keep-out zone (KOZ) was investigated by focusing on the characteristics of the stresses near the surface where the electronic devices are located. The near-surface stresses were characterized by finite element analysis, and the stress effect on carrier mobility was evaluated by considering the piezoresistivity effect near the Si surface. In this paper, the elastic anisotropy of Si was taken into account to evaluate the effect on carrier mobility for both n-and p-channel MOSFET devices aligned along the [100] and [110] directions. The results showed a significant stress effect on carrier mobility, particularly for n-type Si with [100] device alignment and p-type Si with [110] device alignment. Based on these results, the dimension of the KOZ was estimated based on a criterion of 5% change in the carrier mobility. Finally, the effects due to stress interactions in a TSV array and plasticity in Cu vias on the KOZ were investigated. The effect of stress interaction was found to depend on the ratio of the pitch to diameter of the TSV array. When this ratio is less than 5, the stress interaction can increase the size of the KOZ. In contrast, the via material plasticity was found to be useful in reducing the stress level and hence the size of the KOZ.Index Terms-Finite element analysis (FEA), keep-out zone (KOZ), thermomechanical reliability, through-silicon via (TSV), three-dimensional interconnects.
By analyzing the composition dependence of the total amount of Ag photodissolved into amorphous GexS1-x and the fragility of GexS1-x, it is found that at the composition where the amount of Ag photodissolved exhibits a maximum, the fragility shows a minimum, that is, there is an inverse correlation between these two quantities.The possible origin of the correlation found has been discussed by using the constraint theory and the model of fragility proposed by one of the authors.
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