Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration

Abstract

Abstract-Three-dimensional (3-D) integration with throughsilicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in the TSV structures can affect the device performance by degrading carrier mobility and raise serious reliability concerns. In this paper, the effect of thermal stresses in TSV structures on carrier mobility and keep-out zone (KOZ) was investigated by focusing on the characteristics of the stresses near the surface where the electronic devices are located. The near-surface stresses were characterized by finite element analysis, and the stress effect on carrier mobility was evaluated by considering the piezoresistivity effect near the Si surface. In this paper, the elastic anisotropy of Si was taken into account to evaluate the effect on carrier mobility for both n-and p-channel MOSFET devices aligned along the [100] and [110] directions. The results showed a significant stress effect on carrier mobility, particularly for n-type Si with [100] device alignment and p-type Si with [110] device alignment. Based on these results, the dimension of the KOZ was estimated based on a criterion of 5% change in the carrier mobility. Finally, the effects due to stress interactions in a TSV array and plasticity in Cu vias on the KOZ were investigated. The effect of stress interaction was found to depend on the ratio of the pitch to diameter of the TSV array. When this ratio is less than 5, the stress interaction can increase the size of the KOZ. In contrast, the via material plasticity was found to be useful in reducing the stress level and hence the size of the KOZ.Index Terms-Finite element analysis (FEA), keep-out zone (KOZ), thermomechanical reliability, through-silicon via (TSV), three-dimensional interconnects.

S-Parameters Optimization in both Segmented and Unsegmented Insulated TSV upto 40GHz Frequency

“…(1) Figure 3: TSV structure [7] If Z S = Z 0 , that is; impedance of two-port input, no reflections occur and a 1 = 0. If Z L = Z 0 that is; the impedance of two-port output, no reflections occur and a 2 = 0.…”

Characterization of thermal stresses and plasticity in through-silicon via structures for three-dimensional integration

“…The local plasticity is found to reduce the amount of mobility change and thus the size of the KOZ. More details of the KOZ study can be found in a separate publication [9].…”

“…Thermal stresses can arise during fabrication, testing and operation of the TSV structures due to the large mismatch in the coefficient of thermal expansion (CTE) between Cu and Si. The stresses are large enough to cause serious reliability concerns even structural failures in the integrated structure, including TSV extrusion, cracking of Si near the TSV and degradation of device performance [5][6][7][8][9]. Management and mitigation of thermal stresses in the TSV structures require proper stress characterization and modeling analysis.…”

Study on thermal stress and keep-out zone induced by Cu and SiO₂ filled coaxial-annular through-silicon via

“…And then, the carrier mobilities of pMOS and nMOS transistor channels would be affected. Keep-out zone (KOZ) is a common quantitative representation for the impact of thermal stress on transistors [7].…”