Thermomechanical reliability of through-silicon vias in 3D interconnects

Lu, Kuan-Hsun; Ryu, Suk-Kyu; Im, Jungho; Huang, Rui; Ho, Paul S.

doi:10.1109/irps.2011.5784487

Cited by 21 publications

(15 citation statements)

References 9 publications

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“…In practice, the piezoresistivity coefficients for silicon are typically listed in databooks along the crystallographic axes. [3] Using standard techniques for coordinate rotation, the corresponding coefficients in primed axes are obtained as [25] π 11 = (π 11 + π 12 + π 44 ) /2 π 12 = (π 11 + π 12 − π 44 ) /2 π 44 = π 11 − π 12 .…”

Section: A Transistor Low-field Mobility Variation With Stressmentioning

confidence: 99%

“…However, the relative deviation between dotted and solid curves diminishes with temperature. Prior approaches [3]- [5] have considered TSV stress effects ignoring the inherent effects of temperature on mobility and threshold voltage, and have assumed that the worst-case delay occurs at the lowest temperature as seen above, this is not always true.…”

Section: Introductionmentioning

confidence: 99%

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A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

Marella

Sapatnekar

2015

IEEE Trans. VLSI Syst.

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In 3-D ICs, through silicon via (TSV)-induced thermal residual stress impacts several transistor electrical parameters-low-field mobility, saturation velocity, and threshold voltage. These thermal-stress related shifts are coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermallyinduced variations on circuit timing. A biaxial stress model is built, based on a superposition of 2-D axisymmetric and Boussinesq-type elasticity models. The computed stresses and strains are then employed to evaluate transistor mobility, saturation velocity, and threshold voltage. The electrical variations are translated into gate-level delay and leakage power calculations, which are then elevated to circuit-level analysis to thoroughly evaluate the variations in circuit performanceinduced by TSV stress. Index Terms-3-D IC, finite element method (FEM), static timing analysis, through silicon via (TSV).

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Section: A Transistor Low-field Mobility Variation With Stressmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

Marella

Sapatnekar

2015

IEEE Trans. VLSI Syst.

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“…(a) Although the strains in Cu are not high enough to cause failures in perfect TSV structures, the combination of these strains and manufacturing imperfections in TSVs might lead to failures, for instance interfacial delamination, micro-bump cracks, and cracks in TSVs [36,37,38,39].…”

Section: Voids In Tsvsmentioning

confidence: 99%

“…This stress affects not only the mechanical device reliability but also material properties such as carrier mobility [38], which results in timing variations of the devices. Recent studies have reported up tö 10% variations for individual cells [40].…”

Section: Mobility Variation Due To Tsv Stressmentioning

confidence: 99%

Test and debug solutions for 3D-stacked integrated circuits

Deutsch

Chakrabarty

2015

2015 IEEE International Test Conference (ITC)

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Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. TSVs are small copper or tungsten vias that go vertically through the substrate of a die and provide vertical interconnects to a die stacked on top. TSV-based interconnects have benefits in terms of performance, interconnect density, and power efficiency.Testing has been identified as a showstopper for volume manufacturing of 3D-stacked integrated circuits (3D ICs). A number of challenges associated with 3D test need to be addressed before 3D ICs can become economically viable. This dissertation provides solutions to new challenges related to 3D test content, test access, diagnosis and debug.Test content specific to 3D ICs targets defect that occur during TSV manufacturing and stacking process. One example is the effect of thermo-mechanical stress due to TSV fabrication process on the surrounding logic gates. In this dissertation, we analyze these effects and their consequences for delay testing. We provide quantitative results showing that the use of TSV-stress oblivious circuit models for test generation leads to considerable reduction in delay-test quality. We propose a test flow that uses TSV-stress aware circuit models to improve test quality.Another example of 3D-specific test challenge is the testability of TSVs. In this dissertation, we focus on TSV test prior to die bonding, as access to TSVs is limited at this stage. We propose a non-invasive method for pre-bond TSV test that does iv not require TSV probing. The method uses ring oscillators and duty-cycle detectors in order to detect variations in propagation delay of gates connected to a single-sided TSV. Based on the measured variations, we can diagnose the TSV and predict the size of resistive-open and leakage faults using a regression model based on artificial neural networks. In addition, we exploit different voltage levels to increase the robustness of the test method.In order to efficiently deliver test content to structures under test in a 3D stack, 3D design-for-test (DfT) architectures are needed. In this dissertation, we discuss existing 3D-DfT architectures and their optimization. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations and minimizes test time, therefore reducing test cost.Post-silicon debug is a major challenge due to continuously increasing design complexity. Traditional debug methods using signal tracing suffer from the limited capacity of on-chip trace buffers that only allow for signal observation during a short time window. This dissertation proposes a low-cost debug architecture for massive signal tracing in 3D-stacked ICs with wide-I/O DRAM dies. The key idea is to use available on-chip DRAM for trace-data storage, which results in a significant increase of the observation window compared to traditional methods that use trace buffers. ...

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“…These stresses may lead to serious reliability problems such as cracks in silicon substrates [23], [24] or insulators [25], [26]. Even though the stresses are not large enough to lead to die failure, they can cause mobility changes and parametric shifts of transistors, which affect the performance and tolerances of ICs [27]- [33]. Cu pumping in vertical direction may induce delamination of Cu plugs along liner interfaces [25], [34], collapse of microbumps [35], and damage of intermetal dielectrics [36].…”

Section: -D Integration Is Emerging As a Promising Technologymentioning

confidence: 99%

Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

Huang

Pan

Liu

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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Through-silicon vias (TSVs) using benzocyclobutene (BCB)-liners as the insulator have the potential for reducing the TSV capacitances and the thermal expansion stresses. This paper reports the assessments of BCB-liner TSVs with respect to thermal and electrical properties. The C-V and I-V characteristics are measured at room temperature and at an elevated temperature as high as 125°C to characterize the electrical properties of capacitance and leakage current at different temperatures. Some C-V and I-V features associated with BCB-liners are discussed and the mechanisms are analyzed. Thermal cycling between −65°C and 150°C is performed, and the C-V and I-V characteristics are measured before and after thermal cycling to evaluate the thermomechanical stability of the BCB-liners, and the results show that the C-V and I-V properties are improved after thermal cycling. These preliminary results on the electrical and thermal properties of BCB-liner TSVs show that they have good thermal stability.

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Thermomechanical reliability of through-silicon vias in 3D interconnects

Cited by 21 publications

References 9 publications

A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

Test and debug solutions for 3D-stacked integrated circuits

Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

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