Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

With increasing integration density of three-dimensional ICs, temperature is one of the major concern of circuit design, which influences the performance and reliability. In this paper, the parasitic capacitance of tapered TSV (T-TSV) with respect of thermal properties is studied. The concept of the Temperature Coefficient of Capacitance (TCC) is proposed to model the sensitive of TSV capacitance to temperature. It is found that TSV capacitance is sensitive to temperature under high frequency application, and the MOS capacitance variation is the main reason for the change of TSV capacitance and the TCC increases with elevated temperature. Furthermore, the affection of TSV dimensions on TCC are discussed. It is shown that the TCC increases gradually as the TSV radius increases, while the thickness of dielectric layer is the opposite. The cylinder TSV is less thermal sensitive than tapered TSV. This paper provides basis for TSV design considering the temperature effect.

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“…Submitting the R tsv is 5 µm, t die is 0.1 µm into Eq. (9)- (14), the dependence of TCC on temperature are shown in Fig. 4.…”

Section: Temperature Coefficient Of C Tsvmentioning

confidence: 96%

“…A semi-analytical model of the TSV capacitance for elevated operating temperatures has been derived and verified with electrical measurements in [13]. It is found that the capacitance has insignificant changes and the capacitance hysteresis decreases with elevated temperatures of TSVs with BCB-liners in [14].…”

Section: Introductionmentioning

confidence: 92%

Temperature-dependent characterizations on parasitic capacitance of tapered through silicon via (T-TSV)

Liu

Zhu

Liu

et al. 2018

IEICE Electron. Express

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“…As the oxide is the important factor for affecting the electrical performance of Cu/CNT composite TSVs, reducing the oxide capacitance would be the best choice for performance optimization. It is known that the polymer liner, especially BCB material, and even air-gap have been proposed and exploited for TSV applications [21,22] . Therefore, we investigate the impacts of these techniques for performance optimization, as shown in Fig.6.…”

Section: Performance Optimizationmentioning

confidence: 99%

Analysis of Transmission Characteristics of Copper/Carbon Nanotube Composite Through‐Silicon Via Interconnects

Zheng

Zhao

et al. 2019

Chin. j. electron.

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“…Several demonstrations of TSV insulation with low-k polymers deposited by solution techniques were also published. Various deposition technologies, including spin-coating, − spraying, and vacuum-assisted spin coating, − and various polymers (such as benzocyclobutene, , polypropylene carbonate, polybenzoxazole, and polyimide ,, ) have been investigated to achieve conformal polymer covering of trenches. Among these approaches, vacuum-assisted polymer filling has attracted great interest due to its filling ability of high aspect ratio trenches, but in the case of TSV, the conformality is still far from the requirements …”

Section: Introductionmentioning

confidence: 99%

Wafer Scale Insulation of High Aspect Ratio Through-Silicon Vias by iCVD

Jousseaume,

Guerin,

Ichiki

et al. 2024

ACS Appl. Mater. Interfaces

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In microelectronics, one of the main 3D integration strategies consists of vertically stacking and electrically connecting various functional chips using through-silicon vias (TSVs). For the fabrication of the TSVs, one of the challenges is to conformally deposit a low dielectric constant insulator thin film at the surface of the silicon. To date, there is no universal technique that can address all types of TSV integration schemes, especially in the case requiring a low deposition temperature. In this work, an organosilicate polymer deposited by initiated chemical vapor deposition (iCVD) was developed and integrated as an insulating layer for TSVs. Process studies have shown that poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (P(V 3 D 3 )) can present good conformality on high aspect ratio features by increasing the substrate temperature up to 100 °C. The trade-off is a moderate deposition rate. The thermal stability of the polymer has been investigated, and we show that a thermal annealing at 400 °C (with or without ultraviolet exposure) allows the stabilization of the dielectric films by removing residual oligomers. Then, P(V 3 D 3 ) was integrated in high aspect ratio TSV (10 × 100 μm) on 300 mm silicon wafers using a standard integration flow for TSV metallization. Functional devices were successfully fabricated (including daisy chains of 754 TSVs) and electrically characterized. Our work shows that the metallization barrier should be carefully selected to eliminate the appearance of voids at the top corner of the TSV after the Cu annealing step. Moreover, an appropriate integration process should be used to avoid the appearance of cohesive cracks in the liner. This work constitutes a first proof of concept of the use of an iCVD polymer in a quasi-industrial microelectronic environment. It also highlights the benefit of iCVD as a promising technique to deposit conformal dielectric thin films in a microelectronic pilot line environment.

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Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

Cited by 16 publications

References 59 publications

Temperature-dependent characterizations on parasitic capacitance of tapered through silicon via (T-TSV)

Temperature-dependent characterizations on parasitic capacitance of tapered through silicon via (T-TSV)

Analysis of Transmission Characteristics of Copper/Carbon Nanotube Composite Through‐Silicon Via Interconnects

Wafer Scale Insulation of High Aspect Ratio Through-Silicon Vias by iCVD

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