2015
DOI: 10.1109/tvlsi.2014.2335154
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A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

Abstract: In 3-D ICs, through silicon via (TSV)-induced thermal residual stress impacts several transistor electrical parameters-low-field mobility, saturation velocity, and threshold voltage. These thermal-stress related shifts are coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermallyinduced variations on circuit timing. A biaxial stress model is built, based on a superpo… Show more

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Cited by 28 publications
(11 citation statements)
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References 36 publications
(72 reference statements)
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“…The thermal stress at location 1 is mainly attributed to the mismatch of CTE values of Cu and BCB, while others are owing to the metal discontinuity. 24 Figure 6A,B show the maximum temperature T max and thermal stress F max of the PF-TSV array for different parameter of polymer via d poly and TSV pitch p, respectively. As d poly increases from 30 to 50 μm, T max and F max increase by 2.6% and 13.7%, respectively.…”
Section: Static State Analysismentioning
confidence: 99%
“…The thermal stress at location 1 is mainly attributed to the mismatch of CTE values of Cu and BCB, while others are owing to the metal discontinuity. 24 Figure 6A,B show the maximum temperature T max and thermal stress F max of the PF-TSV array for different parameter of polymer via d poly and TSV pitch p, respectively. As d poly increases from 30 to 50 μm, T max and F max increase by 2.6% and 13.7%, respectively.…”
Section: Static State Analysismentioning
confidence: 99%
“…These variations can be mitigated by implementation of multiple clock domains [47]. Note that variations are exacerbated in interposer stacks and TSVbased 3D ICs, mainly due to thermo-mechanical stress [48].…”
Section: Clock Deliverymentioning
confidence: 99%
“…the simulation of TSV arrays-they have been successfully modeled using manifold approaches: as multi-port components along with S-parameters for simulation of signal coupling [17,18,102]; as MIMO channels to regulate equalization of such coupling [103]; via superposition of TSV's stress components to capture their impact on power and/or timing [48,96]; and via superposition of stress components to determine thermo-mechanical stress itself [9,96,100]. The automated generation of such models, also for other components than TSV arrays, remains an open challenge [104].…”
Section: Multi-physics Simulation and Verificationmentioning
confidence: 99%
“…However, being relatively accurate, FEM based methods cannot be used for DTM due to their large computing costs. The analytical stress models have also been developed [8], [4], [10] to analyze thermal stress behaviors around TSV structures. However, these methods assume simple TSV structures in order to simplify the mathematical equation derivation steps, and generates model with relatively large error.…”
Section: Introductionmentioning
confidence: 99%
“…From [10], it is known that the stress in the Z direction is 0, and as a result, we only need to analyze the stress in the 2-D plane. Fig.…”
Section: Introductionmentioning
confidence: 99%