A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

Marella, Sravan K.; Sapatnekar, Sachin S.

doi:10.1109/tvlsi.2014.2335154

Cited by 28 publications

(11 citation statements)

References 36 publications

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“…The thermal stress at location 1 is mainly attributed to the mismatch of CTE values of Cu and BCB, while others are owing to the metal discontinuity. 24 Figure 6A,B show the maximum temperature T max and thermal stress F max of the PF-TSV array for different parameter of polymer via d poly and TSV pitch p, respectively. As d poly increases from 30 to 50 μm, T max and F max increase by 2.6% and 13.7%, respectively.…”

Section: Static State Analysismentioning

confidence: 99%

Multiphysics characterization of polymer‐filled through‐silicon vias (PF‐TSVs) for three‐dimensional integration

Jin

Zhao

Wang

et al. 2018

Int J Numerical Modelling

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To increase the density of input/output connections, the polymer-filled through-silicon vias (PF-TSVs) were proposed recently. To analyze the reliability of the PF-TSVs, multiphysics characterization is conducted in this paper. The time-domain finite-element method is used to cosolve the heat conduction and thermal stress equations. Temperature-dependent materials' parameters such as thermal conductivity, coefficient of thermal expansion, and Young's modulus, are treated appropriately. Based on the in-house developed timedomain finite-element method algorithm, the temperature and thermal stress distributions of the PF-TSV array and channel are evaluated. Transient thermo-mechanical responses are captured and studied in detail for the PF-TSV array and channel with different periodic voltage pulses applied. It is anticipated that this study provides certain guidance for the design and applications of PF-TSVs.

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Section: Static State Analysismentioning

confidence: 99%

Multiphysics characterization of polymer‐filled through‐silicon vias (PF‐TSVs) for three‐dimensional integration

Jin

Zhao

Wang

et al. 2018

Int J Numerical Modelling

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“…These variations can be mitigated by implementation of multiple clock domains [47]. Note that variations are exacerbated in interposer stacks and TSVbased 3D ICs, mainly due to thermo-mechanical stress [48].…”

Section: Clock Deliverymentioning

confidence: 99%

“…the simulation of TSV arrays-they have been successfully modeled using manifold approaches: as multi-port components along with S-parameters for simulation of signal coupling [17,18,102]; as MIMO channels to regulate equalization of such coupling [103]; via superposition of TSV's stress components to capture their impact on power and/or timing [48,96]; and via superposition of stress components to determine thermo-mechanical stress itself [9,96,100]. The automated generation of such models, also for other components than TSV arrays, remains an open challenge [104].…”

Section: Multi-physics Simulation and Verificationmentioning

confidence: 99%

Physical Design Automation for 3D Chip Stacks

Knechtel¹,

Lienig²

2016

Proceedings of the 2016 on International Symposium on Physical Design

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The concept of 3D chip stacks has been advocated by both industry and academia for many years, and hailed as one of the most promising approaches to meet ever-increasing demands for performance, functionality and power consumption going forward. However, a multitude of challenges has thus far obstructed large-scale transition from "classical" 2D chips to stacked 3D chips. We survey major design challenges for 3D chip stacks with particular focus on their implications for physical design. We also derive requirements for advances in design automation, such as the need for a unified workflow. Finally, we outline current promising solutions as well as areas needing further research and development. bly design kit; design standards 2. 3D-CHIP STACKING OPTIONS AND HIGH-LEVEL DESIGN CHALLENGES 3D-chip stacking falls into four categories (Fig. 2): (i) package stacking, (ii) interposer stacks, (iii) through-silicon via (TSV)based 3D ICs, and (iv) monolithic 3D ICs. Each option has its This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike International 4.0 License.

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“…However, being relatively accurate, FEM based methods cannot be used for DTM due to their large computing costs. The analytical stress models have also been developed [8], [4], [10] to analyze thermal stress behaviors around TSV structures. However, these methods assume simple TSV structures in order to simplify the mathematical equation derivation steps, and generates model with relatively large error.…”

Section: Introductionmentioning

confidence: 99%

“…From [10], it is known that the stress in the Z direction is 0, and as a result, we only need to analyze the stress in the 2-D plane. Fig.…”

Section: Introductionmentioning

confidence: 99%

Fast stress analysis for runtime reliability enhancement of 3D IC using artificial neural network

Zhang

Wang

Tan

2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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Heat dissipation and the related thermal-mechanical stress problems are the major obstacles in the development and commercializing process of 3D ICs. Dynamic thermal management (DTM) techniques can be used to alleviate such problems and enhance the reliability of 3D ICs. However, the time varying stress information is hard to obtain at runtime which limites the effectiveness of DTM. In this paper, we propose a fast stress analysis method for runtime usage. The new method builds artificial neural network (ANN) model by training offline using thermal and stress data. Next, the ANN model is used to generate important stress information, such as maximum stress around each TSV, for DTM methods at runtime. In order to improve the stress estimation accuracy and speed, specially designed input selection plans are proposed and implemented for ANN model generation. Experiments with different configurations of ANN models show that the new method is able to estimate important stress information at extremely fast speed with good accuracy for runtime 3D IC reliability enhancement usage. 17th Int'l Symposium on Quality Electronic Design

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A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

Cited by 28 publications

References 36 publications

Multiphysics characterization of polymer‐filled through‐silicon vias (PF‐TSVs) for three‐dimensional integration

Multiphysics characterization of polymer‐filled through‐silicon vias (PF‐TSVs) for three‐dimensional integration

Physical Design Automation for 3D Chip Stacks

Fast stress analysis for runtime reliability enhancement of 3D IC using artificial neural network

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