Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects

Abstract

Abstract-Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, 3-D integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Among others, thermomechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effects of thermally induced stresses on the interfacial reliability of TSV structures. First, 3-D distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semianalytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results from finite element analysis (FEA). The stress analysis suggests interfacial delamination as a potential failure mechanism for the TSV structure. An analytical solution is then obtained for the steady-state energy release rate as the upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. With these results, the effects of the TSV dimensions (e.g., via diameter and wafer thickness) on the interfacial reliability are elucidated. Furthermore, the effects of via material properties and dielectric buffer layers are discussed.

Characterization of thermal stresses and plasticity in through-silicon via structures for three-dimensional integration

“…Via extrusion, or pop-up, is a reliability issue in 3D integration in which Cu extrudes from the wafer surface to damage the interconnect structures above the vias [5]. A previous study has shown that stress-induced interfacial delamination could result in via extrusion [7]. However, in subsequent investigations including this study, via extrusion was observed without evidence of delamination.…”

“…Thermal stresses can arise during fabrication, testing and operation of the TSV structures due to the large mismatch in the coefficient of thermal expansion (CTE) between Cu and Si. The stresses are large enough to cause serious reliability concerns even structural failures in the integrated structure, including TSV extrusion, cracking of Si near the TSV and degradation of device performance [5][6][7][8][9]. Management and mitigation of thermal stresses in the TSV structures require proper stress characterization and modeling analysis.…”

“…In addition, the method requires special facility that is not easily accessible. Numerical analyses such as finite element analysis (FEA) are commonly used to calculate the magnitude and distribution of stresses in TSV structures [14][15][16]. This method allows the study of complex structures without special experimental facilities.…”

Thermal stress induced delamination of through silicon vias in 3-D interconnects

“…The difference between two opposite thermal loads is further illustrated in Figure 2. The analytical solutions for steady-state TSV delamination have been derived for both the cooling and heating conditions [6]. Consider an isolated, infinitely long TSV embedded in an infinite matrix with a circumferential crack propagating along the axial direction under a thermal load.…”

Thermomechanical characterization and modeling for TSV structures

“…Based on the results from the microstructure analysis, the mechanisms underlying the linear and nonlinear temperature-curvature behavior of the TSV specimen are discussed. The local stress distribution near the Si surface around the Cu vias is important on device performance and interfacial reliability [7,8]. This was measured by micro-Raman spectroscopy [9].…”