Carbon nanotubes ͑CNTs͒ are considered a promising material for interconnects for future generation microchips. The integration of vertical CNT in a processing environment is evaluated in this work. Extrapolated performances of CNT-based interconnects are compared with existing technologies at different hierarchy levels including the limitations of present deposition methods for copper and tungsten. For practical implementation, CNT bundles were selectively grown into contact holes using physical vapor deposited and electrochemical deposited cobalt or nickel catalysts. A polishing step was used to control the CNT length after embedding the CNT into an oxide matrix. A CNT metal decoration method based on electrodeposition is presented, which can be used to assess the yield of electrically conductive CNT as well as to form top contacts for electrical characterization. Finally, the importance of having suitable and robust structures for evaluating the integration process is highlighted after the electrical characterization of CNT in a nanoprober station.

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We report on aggressively scaled RMG-HKL planar and multigate FinFET-based devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF 6) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced J G and noise values can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF 6 , without EOT penalty; 2) SF 6 also enables improved mobility and reduced N it down to narrower fin devices (W Fin ≥5nm), mitigating the impact of fin patterning, fin corners and fin sidewalls crystal orientations, while allowing a simplified dual-EWF metal CMOS scheme suitable for both device architectures and which maximizes the space for gate metallization; 3) PDA also yields lower PMOS |V T |, and substantially improved NBTI lifetime and hot-carrier (HC) immunity thanks to its reduction of bulk defects which is shown to be key in the (sub-)1nm EOT regime.

We demonstrate electrically functional 0.099μm 2 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) highk/metal gate FinFETs with L g~4 0nm, 12-17nm wide Fins, and cell β ratio~1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, ≥30nm-wide contacts. SRAM cell with SNM>10%V DD down to 0.4V, and healthy electrical characteristics for the cell transistors [SS~80mV/dec, DIBL~50-80mV/V, and V Tlin ≤0.2V (PMOS), V Tlin~0 .36V (NMOS)] are reported.

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