The availability of high density TSVs depends on how smart we miniaturize the interconnect dimension in 3D IC package. A number of considerations include controllable TSV aspect ratio, pitch, and material selection. The International Technology Roadmap for Semiconductors (ITRS) has proposed scaling of TSV diameter down to as low as 2 m in the future. However, with TSV scaling, the resistance of the TSV increases significantly. Carbon nanotubes (CNTs) could be a potential alternative material to Cu for VLSI interconnects applications, including TSV, due to their outstanding electrical, mechanical, and thermal properties. Here, we demonstrate a method to integrate carbon nanotubes (CNTs)-filled TSV under 5 μm diameter that are connected by metal-lines at the bottom and show the facile route of fabrication at low temperature regime. The process challenges are highlighted.
Keywords-Carbon nanotube, Through-silicon via, 3D-IC, Wafer bondingI.