Process control & integration options of RMG technology for aggressively scaled devices

Optimized material solutions for advanced DRAM peripheral transistors

“…. We have fabricated PMOS and NMOS RMG gate stacks traditionally used for logic applications , which are illustrating why we need a specific gate stack optimization for DRAMs. These stacks are obtained by using two different TiN deposition techniques (needed for the ESL and eWF control), with a thicker SiO 2 interfacial layer to account for the stronger gate leakage requirements.…”

“…Another consideration that has to be taken into account is related to the ESL. It has been shown that TiN is capable of guaranteeing the ESL functionality required to prevent the excess of Al diffusion , however, an increase of the metal gate thickness generates a significant unwanted work function increase (Fig. ).…”

Low-Frequency-Noise-Based Oxide Trap Profiling in Replacement High-κ/Metal-Gate pMOSFETs

“…[4][5][6][7][8] There are two ways to maintain a good-quality interface in a HKlast approach: firstly, this can be achieved by a careful removal of the dummy oxide and an optimized surface cleaning prior to the formation of the interfacial oxide layer (SiO 2 IL) and Atomic Layer Deposition (ALD) of the HfO 2 . 9 It has been observed that a similar interface and gate oxide quality is obtained using different pre-deposition cleans, i.e., an HF etch; a plasma etch or the combination of the two. 3,9 A second approach is based on the application of a post-ALD thermal anneal or an SF 6 -plasma treatment.…”

“…9 It has been observed that a similar interface and gate oxide quality is obtained using different pre-deposition cleans, i.e., an HF etch; a plasma etch or the combination of the two. 3,9 A second approach is based on the application of a post-ALD thermal anneal or an SF 6 -plasma treatment. 9,10 It is known from the past that introduction of F in the gate oxide can reduce the density of active border traps (BTs) and interface states, [11][12][13][14][15][16][17] which has recently also been validated for high-κ-last pMOSFETs through LF noise studies.…”

“…3,9 A second approach is based on the application of a post-ALD thermal anneal or an SF 6 -plasma treatment. 9,10 It is known from the past that introduction of F in the gate oxide can reduce the density of active border traps (BTs) and interface states, [11][12][13][14][15][16][17] which has recently also been validated for high-κ-last pMOSFETs through LF noise studies. 18 The aim of the present paper is to report on the LF noise and the corresponding trap density profiles of planar HK/MG-last pMOSFETs with an Equivalent Oxide Thickness (EOT) of ∼1 nm.…”