Low-Frequency-Noise-Based Oxide Trap Profiling in Replacement High-κ/Metal-Gate pMOSFETs

Abstract

Low-frequency noise is studied in planar high-κ/metal-gate (HK/MG) last pMOSFETs in order to assess the impact of a post-HfO2 deposition SF6-plasma or heat-treatment on the oxide trap density and profile. It is shown that the gate oxide quality is improved by lowering the active border trap density for both approaches. At the same time, a detailed analysis of the frequency exponent of the flicker noise spectra reveals that in the case of the SF6-plasma, the reduction of the active border trap density occurs more efficiently deeper in the high-κ layer, while the opposite holds for the annealed devices, i.e., a lower trap density is found closer to the interfacial SiO2 layer.

Low-Frequency Noise Assessment of the Oxide Trap Density in Thick-Oxide Input-Output Transistors for DRAM Applications

“…7. These trap densities are about one decade lower than typically found in high-κ materials, 8,9,12,13 so that the present gate stacks are somewhere intermediate pure SiO 2 and pure HfO 2 from a viewpoint of oxide trap density. The blue HKMG curve in Fig.…”

“…In the case where a pronounced trap density profile is present, one should investigate the whole frequency range in more detail, as already discussed elsewhere. 12,13 Assuming elastic tunneling, the frequency axis of a noise spectrum can be converted into a tunneling depth, using:…”

“…In the case where a pronounced trap density profile is present, one should investigate the whole frequency range in more detail, as already discussed elsewhere. 12,13 Assuming elastic tunneling, the frequency axis of a noise spectrum can be converted into a tunneling depth, using: 14,15 z = 1 α t ln 1 2πf τ 0 [3] In Eq. 3, τ 0 is the Shockley-Read-Hall recombination lifetime at the Si/SiO 2 interface, usually on the order of 10 −10 s. 16 The oxide trap density profiles calculated from a spectrum at a gate voltage around V T for each wafer are represented in Fig.…”

Low Frequency Noise Analysis of Impact of Metal Gate Processing on the Gate Oxide Stack Quality

“…[38][39][40][41][42][43][44][45][46] The investigated pMOSFETs had a 0.6 nm chemical (ozone) SiO 2 , formed after standard diluted HF clean, 36 ALD cycles of HfO 2 (∼1.8 nm thickness) and TiN gate followed by a fill metal. 28 As illustrated in Fig. 6, showing for the different process options the experimental data and median value, optimal noise performance was found for a 3 to 6 min SF 6 treatment, resulting in a clear reduction of the average noise PSD and the device-to-device variation.…”

“…Devices with different architectures (planar, Fin-FET and NanoWire (NW) FETs) will be addressed in addition to the gate first versus gate last (or replacement metal gate -RMG) integration. [26][27][28]…”