Engineering the effective work function of scaled-down devices is commonly achieved by the implementation of capping layers in the gate stack. Typical cap layers are Al 2 O 3 for pMOSFETs and La-oxide or Mg for nMOSFETs. Besides introducing a dipole layer at the SiO 2 /high-κ interface, the in-diffusion of the metal ions may lead to either passivation or generation of traps in the SiO 2 /high-κ layer. This paper uses low frequency noise studies to determine the impact of capping layers on the quality of the SiO 2 /HfO 2 gate stacks. The influence on the trap profiles of different types of cap layers, different locations of the cap layer (below or on top of the HfO 2 dielectric) and the impact of different thermal budgets, typically used for the fabrication of Dynamic Random Access Memory (DRAM) logic devices, are investigated. The differences between several metal oxides are outlined and discussed.