The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.
This paper represents the lowest growth temperature for silicon nano-wires (SiNWs) via a vapour-liquid–solid method, which has ever been reported in the literature. The nano-wires were grown using plasma-enhanced chemical vapour deposition technique at temperatures as low as 150°C using gallium as the catalyst. This study investigates the structure and the size of the grown silicon nano-structure as functions of growth temperature and catalyst layer thickness. Moreover, the choice of the growth temperature determines the thickness of the catalyst layer to be used.The electrical and optical characteristics of the nano-wires were tested by incorporating them in photovoltaic solar cells, two terminal bistable memory devices and Schottky diode. With further optimisation of the growth parameters, SiNWs, grown by our method, have promising future for incorporation into high performance electronic and optical devices.
Presently, there is a rapid growth of interest in the area of flexible electronics. Benefits such as light weight, durability and low-cost are among the most appealing aspects. However, the high temperatures throughout the fabrication processes are still the main hurdle. In this study, the deposition of silicon nanowires (SiNWs) at low temperature (300˚C) using Tin (Sn) catalyst is studied. Silicon nanostructures have been the centre of research for many years for a number of applications in different areas. Chemical Vapour Deposition (CVD) and other industrial deposition techniques, for the growth of crystalline silicon microand nano-structures use high temperatures and therefore are not compatible with temperature sensitive substrates. This work utilises a low temperature deposition method for the growth of SiNWs and creates a leeway to use flexible plastic sheets as substrates. The silicon nanowires were deposited by exploiting the Vapour-Liquid-Solid (VLS) material growth mechanism using Plasma Enhanced Chemical Vapour Deposition (PECVD) technique. The suitability of these structures, as an information storage material, for future flash and two terminals non-volatile memory devices are investigated. Strong charge storage behaviour with a retention time up to 5 hours was observed showing great potential for the future memory candidate.
In the recent years a notable progress in the miniaturisation of electronic devices has been achieved in which the main component that has shown great interest is electronic memory. However, miniaturisation is reaching its limit. Alternative materials, manufacturing equipment and architectures for the storage devices are considered. In this work, an investigation on the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices is presented. Silicon nanostructures have attracted attention due to their small size, interesting properties and their potential integration into electronic devices. The two-terminal memory devices presented in this work, have a simple structure of silicon nanowires sandwiched between dielectric layers (silicon nitride) on glass substrate with thermally evaporated aluminium bottom and top contacts. The silicon nanostructures and the dielectric layer were deposited by Plasma Enhanced Chemical Vapour Deposition (PECVD) technique. The electrical behaviour of the memory cell was examined by Current-Voltage (I-V), data retention time (Current-time) and write-read-erase-read measurements. Metal-Insulator-Semiconductor (MIS) structures were also prepared for further analysis. The same silicon nanowires were embedded into the MIS capacitors and Capacitance-Voltage (C-V) analysis was conducted. Strong I-V and C-V hysteresis as well as an electrical bistability were detected. The memory effect is observed by this electrical bistability of the device that was able to switch between high and low conductivity states.
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