Thin‐film transistors (TFTs) based on amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) have attracted vast attention for use in organic light‐emitting diode (AMOLED) displays due to their high electron mobility and large current on–off ratio. Although amorphous oxide semiconductors show considerably less threshold voltage (Vth) variation than poly‐silicon, large‐area processing and degradation effects can impede the characteristic parameters of a‐IGZO TFTs, which manifests in an uneven brightness distribution across the display panel. Such Vth variations are usually reduced by additional compensation circuits consisting of TFTs and capacitors. Herein, a new approach to compensate such variabilities is demonstrated: the integration of a programmable ferroelectric (FE) film in the gate stack of the TFT. This simplifies the complexity of the pixel cell and potentially minimizes the need for compensation circuits, which is crucial for transparent displays. To test this new approach, fully integrated FE‐TFTs (i.e., with vias contacting a structured bottom gate electrode from the top) based on a‐IGZO and FE hafnium‐zirconium oxide (HZO) are developed. A single low‐temperature post‐fabrication treatment at 350 °C for 1 h in air is used to simultaneously crystallize the HZO film in the FE phase and to reduce the number of defects in the a‐IGZO channel. The structural and electrical characterizations provide comprehensive guidance for the design of effective FE‐TFT gate stacks and device geometries. An accurate control of the polarization state and linear switching between multiple intermediate states is shown by using programming pulses of various amplitudes and widths. Furthermore, a direct correlation between the channel length and the applied pulse width for programming is observed.

Note: This paper is part of the Special Topic on Materials and Devices Utilizing Ferroelectricity in Halfnium Oxide.

The ferroelectric properties of hafnium oxide films are strongly influenced by the crystallization process due to the interaction of thermodynamics, kinetics, and mechanical stress. In this work, the influence of annealing temperature on the crystallographic properties and microstructure of Si-doped hafnium oxide thin films as well as their ferroelectric properties are investigated by X-ray diffraction, transmission Kikuchi diffraction, and electrical characterization. The findings reveal the emergence of a [100] and [110] out-of-plane texture for metal−ferroelectric− metal (MFM) and metal−ferroelectric−insulator−semiconductor (MFIS) capacitor structures with increasing annealing temperature, respectively. In combination with observed stress relaxation at higher temperatures and the evolution of the wake-up behavior, insights into the crystallization process and the influence of the interplay of microstructure and stress on the ferroelectric properties of hafnium oxide thin films are given.

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Reliability is a central aspect of hafnium oxide-based ferroelectric field effect transistors (FeFETs), which are promising candidates for embedded non-volatile memories. Besides the device performance, understanding the evolution of the ferroelectric behaviour of hafnium oxide over its lifetime in FeFETs is of major importance for further improvements. Here, we present the impact of the interface layer in FeFETs on the cycling behaviour and retention of ferroelectric silicon-doped hafnium oxide. Thicker interfaces are demonstrated to reduce the presence of antiferroelectric-like wake-up effects and to improve endurance. However, they show a strong destabilisation of one polarisation state in terms of retention. In addition, measurements of the Preisach density revealed additional insight in the wake-up effect of these metal-ferroelectric-insulator-semiconductor (MFIS) capacitors. Graphic abstract

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