In this paper, the reliability of through-silicon via (TSV) daisy chains under thermal cycling conditions was examined. The electrical resistance of TSV daisy chains was found to increase with the number of thermal cycles, due to thermally induced damage leading to the formation and growth of defects. The contributions of each identified damage type to the change in the electrical resistance of the TSV chain were evaluated by electrical modeling. Thermo-mechanical modeling showed a good correlation between the observed damage locations and the simulated stress-concentration regions of the TSV.Index Terms-Failure analysis, finite element analysis, threedimensional integrated circuits, through-silicon vias.
This paper reports on thermal-mechanical failures of through-silicon-vias (TSVs), in particular, for the first time, the protrusions at the TSV backside, which is exposed after wafer bonding, thinning and TSV revealing. Temperature dependence of TSV protrusion is investigated based on widerange thermal shock and thermal cycling tests. While TSV protrusion on the TSV frontside is not visible after any of the tests, protrusions on the backside are found after both thermal shock tests and thermal cycling tests at temperatures above 250 o C. The average TSV protrusion height increases from ~0.1 μm at 250 ºC to ~0.5 μm at 400 ºC and can be fitted to an exponential function with an activation energy of ~0.6eV, suggesting a Cu grain boundary diffusion mechanism.
One of the main causes of failure during the lifetime of microelectronics devices is their exposure to fluctuating temperatures. In this work, synchrotron-based X-ray micro-diffraction is used to study the evolution of stresses in copper through-silicon via (TSV) interconnects, “as-received” and after 1000 thermal cycles. For both test conditions, significant fluctuations in the measured normal and shear stresses with depth are attributed to variations in the Cu grain orientation. Nevertheless, the mean hydrostatic stresses in the “as-received” Cu TSV were very low, at (16 ± 44) MPa, most likely due to room temperature stress relaxation. In contrast, the mean hydrostatic stresses along the entire length of the Cu TSV that had undergone 1000 thermal cycles (123 ± 37) MPa were found to be eight times greater, which was attributed to increased strain-hardening. The evolution in stresses with thermal cycling is a clear indication that the impact of Cu TSVs on front-end-of-line (FEOL) device performance will change through the lifetime of the 3D stacked dies, and ought to be accounted for during FEOL keep-out-zone design rules development.
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