Backside TSV protrusion induced by thermal shock and thermal cycling

Zhang, Dingyou; Hummler, Klaus; Smith, Larry; Lu, James

doi:10.1109/ectc.2013.6575757

Cited by 28 publications

(23 citation statements)

References 22 publications

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“…Thermal-mechanical failures of TSVs including the TSV protrusions from the die surface are studied in [Zhang13]. The TSV protrusions are observed after wafer bonding, thinning, and TSV revealing.…”

Section: Temperature Cyclingmentioning

confidence: 99%

“…Further temperature cycling will have almost no effect on the TSV length, afterwards. The TSV protrusion can be further exacerbated by the electrical current it carries [Kumar12,Zhang13]. Therefore, operating the IC during this procedure (letting the current to flow) speeds up the cycling acceleration.…”

Section: Preliminariesmentioning

confidence: 99%

“…However, after a few temperature-cycles an increase in the TSV length may be observed. The TSV length will continue to increase with the number of cycles [Kumar12,Zhang13]. After a certain amount of temperature cycling, the TSV length approaches a maximum level.…”

Section: Preliminariesmentioning

confidence: 99%

“…These effects are worsened by temperature cycling. Furthermore, some other defects, including resistive opens and stress induced carrier mobility reduction, can also be worsened by temperature cycling [Kumar12, Okoro14,Zhang13].…”

Section: Chapter 6 Integrated Temperaturecycling Acceleration and Testmentioning

confidence: 99%

“…TSV protrusion on the backside is affected by temperature cycling. Protrusion magnitude can be fitted to an exponential model which suggests a grain boundary diffusion mechanism might be behind it [Zhang13].…”

Section: Temperature Cyclingmentioning

confidence: 99%

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Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deepsubmicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.Advanced SoCs manufactured as 3D-stacked-ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be accelerated using gradientbased, burn-in like operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. Schedule-based techniques that enforces the temperature-gradients for burn-in like operations and delay testing are proposed in this thesis. Abstract iiThe last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safetycritical systems to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced.All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC'02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the test costs. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the test schedule generation time by more than half.iii Populärvetenskaplig sammanfattningMånga banbrytande dator-och elektronikprodukter drivs...

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Section: Temperature Cyclingmentioning

confidence: 99%

Section: Preliminariesmentioning

confidence: 99%

Section: Preliminariesmentioning

confidence: 99%

Section: Chapter 6 Integrated Temperaturecycling Acceleration and Testmentioning

confidence: 99%

Section: Temperature Cyclingmentioning

confidence: 99%

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Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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Impact of polyimide liner on high-aspect-ratio through-silicon-vias (TSVs): electrical characteristics and copper protrusion

et al. 2017

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A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs

2015

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In a modern three-dimensional integrated circuit (3D IC), vertically stacked dies are interconnected using through silicon vias. 3D ICs are subject to undesirable temperature-cycling phenomena such as through silicon via protrusion as well as void formation and growth. These cycling effects that occur during early life result in opens, resistive opens, and stress induced carrier mobility reduction. Consequently these early-life failures lead to products that fail shortly after the start of their use. Artificially-accelerated temperature cycling, before the manufacturing test, helps to detect such early-life failures that are otherwise undetectable. A test-ordering based temperaturecycling acceleration technique is introduced in this paper that integrates a temperature-cycling acceleration procedure with pre-, mid-, and post-bond tests for 3D ICs. Moreover, it reduces the need for costly temperature chamber based temperature-cycling acceleration methods. All these result in a reduction in the overall test costs. The proposed method is a test-ordering and schedule based solution that enforces the required temperature cycling effect and simultaneously performs the tests whenever appropriate. Experimental results demonstrate the efficiency of the proposed technique.

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Backside TSV protrusion induced by thermal shock and thermal cycling

Cited by 28 publications

References 22 publications

Thermal Issues in Testing of Advanced Systems on Chip

Thermal Issues in Testing of Advanced Systems on Chip

Impact of polyimide liner on high-aspect-ratio through-silicon-vias (TSVs): electrical characteristics and copper protrusion

A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs

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