A quantum transport simulator, Schrödinger equation Monte Carlo (SEMC) in three dimensions, is presented that provides a rigorous yet reasonably computationally efficient quantum mechanical treatment of real scattering processes within quantum transport simulations of nanoscale three-dimensional (3D) metal oxide semiconductor field-effect transistor (MOSFET) geometries such as quantum wire and multigate field-effect transistors. This work represents an extension of earlier versions of SEMC for simulating quantum transport and scattering in systems with relatively simpler quasi-one-dimensional and quasi-two-dimensional geometries such as quantum-cascade lasers (via SEMC in one dimension) and silicon-on-insulator or dual-gate MOSFETs (via SEMC in two dimensions), respectively. However, the limiting computational considerations can be significantly different. The SEMC approach represents a variation in nonequilibrium Green’s function techniques with scattering as well as carrier injection into the simulation region treated via Monte Carlo techniques. Scattering mechanisms include intravalley and intervalley scatterings, intrasubband and intersubband scatterings via acoustic and optical phonons, and, in the former case, surface roughness scattering. SEMC-3D simulations of a silicon omega-gate nanoscale n-channel MOSFET are provided to illustrate the modeling technique as well as the complexity of scattering effects in such nanoscale devices.
In this study, novel n-type double-gate (DG) junction-less (J-less) polycrystalline silicon (poly-Si) nanostrip transistors with different channel doping concentrations (N C ) have been fabricated and investigated. The effects of channel doping concentration on device characteristics were examined comprehensively in this work. The experimental data show that as the channel doping concentration of the J-less device increases, the threshold voltage (V TH ) becomes more negative. Besides, the drain-induced barrier lowering and the subthreshold swing of the J-less transistors become larger as the channel doping increases. We also found that as the channel doping increases, the off-current (I OFF ) increases and the on-current (I ON ) actually decreases due to the doping-dependent mobility degradation. The conduction mechanisms under different channel doping concentrations were also investigated by TCAD simulation. The experimental results suggest that the n-type DG nanostrip J-less transistor with lower channel doping will have superior device characteristics.
In this study, we derive an analytical model of an electric potential of a double-gated (DG) fully depleted (FD) junctionless (J-less) transistor by solving the two-dimensional Poisson's equation. On the basis of this two-dimensional electric potential model, subthreshold current and swing can be calculated. Threshold voltage roll-off can also be estimated with analytical forms derived using the above model. The calculated results of electric potential, subthreshold current and threshold voltage roll-off are all in good agreement with the results of technology computer aided design (TCAD) simulation. The model proposed in this paper may help in the development of a compact model for simulation program with integrated circuit emphasis (SPICE) simulation and in providing deeper insights into the characteristics of short-channel J-less transistors.
In this study, novel independent double-gate (IDG) junction-less (J-less) polycrystalline silicon (poly-Si) nano-strip transistors have been fabricated and investigated. Inversion-mode (IM) IDG poly-Si nano-strip transistors with the undoped channel have also been fabricated for comparison. The experimental data show the superior on-state current of J-less transistors over that of IM transistors mainly due to the reduction of the channel resistance (R ch). However, the drain-induced barrier lowering of the J-less transistors is larger than that of IM transistors but the double-gate (DG) configuration can mitigate this problem to some extent. Besides, the subthreshold swing and its fluctuation of the J-less transistors are worse than those of IM transistors under the single-gate operation. Fortunately, this issue can be significantly improved by the aid of DG configuration according to our experimental results. We also demonstrate the possibility of changing the threshold voltage (V th) under IDG operation for the J-less IDG nano-strip transistors.
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