The effects of channel doping concentration for n-type junction-less double-gate poly-Si nanostrip transistors

Abstract

In this study, novel n-type double-gate (DG) junction-less (J-less) polycrystalline silicon (poly-Si) nanostrip transistors with different channel doping concentrations (N C ) have been fabricated and investigated. The effects of channel doping concentration on device characteristics were examined comprehensively in this work. The experimental data show that as the channel doping concentration of the J-less device increases, the threshold voltage (V TH ) becomes more negative. Besides, the drain-induced barrier lowering and the subthreshold swing of the J-less transistors become larger as the channel doping increases. We also found that as the channel doping increases, the off-current (I OFF ) increases and the on-current (I ON ) actually decreases due to the doping-dependent mobility degradation. The conduction mechanisms under different channel doping concentrations were also investigated by TCAD simulation. The experimental results suggest that the n-type DG nanostrip J-less transistor with lower channel doping will have superior device characteristics.

Extraction of mobility and Degradation coefficients in double gate junctionless transistors

“…For instant with L g scaling down from 1 μm to 80 nm, 19% of reduction in μ bulk has been observed for N d =5×10 18 cm −3 whereas, for N d =2×10 19 cm −3 the reduction in μ bulk is 38%. This shows that JL transistors with higher doping levels are prone to SCEs compared to lower N d levels [33]. Similar to μ bulk , the dependence of mobility with L g scaling has also been observed for μ acc , where mobility degradation is more prominent due to the influence of shorter gate length.…”

Device design guideline for junctionless gate-all-around nanowire negative-capacitance FET with HfO2-based ferroelectric gate stack

“…For both cases, V th becomes lower as N increases. This indicates that the off-state leakage current increases with higher N values, and a higher N requires more negative bias to prevent the leakage current [12]. Figure 6(b) shows SS avg and SS min of both JL-NWFET and NC-JL-NWFET, wherein different trends are observed.…”

Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

“…The old MOSFET transistors used in the past were made of two p-n junctions with an effective channel length designed between them. MOSFET technology has reached its limits from the point of view of miniaturization, imposed by the gate tunneling current and the adverse short channel effects (SCEs) [1,2]. This is why many new multiple gate structures such as double-gate (DG) [3], triple-gate (TG) [4], -gate [5], -gate [6], quadruple-gate (QG) and surrounding gate MOSFETs [7,8] have become coveted research topics because of their high gate control ability and their high scaling [6].…”