The perovskite SrHfO3 can be a potential candidate among the high-permittivity materials for gate oxide replacement in future metal-oxide semiconductor field-effect transistor technology. Thin films of SrHfO3 were grown by molecular beam epitaxy and compared with SrTiO3 films. Their optical properties were investigated using spectroscopic ellipsometry and analyzed with respect to their structural properties characterized by x-ray diffractometry, atomic force microscopy, and transmission electron microscopy. A band gap of Eg=6.1±0.1eV is measured optically, which renders this material better suited for gate dielectric applications than SrTiO3 with Eg∼3.4eV. At similar equivalent oxide thickness, SrHfO3 also exhibits lower gate leakage current than SrTiO3 does.

Thin epitaxial films of the high-perovskite SrHfO 3 were grown by molecular beam epitaxy on Si(100) and investigated by ellipsometry and X-ray photoelectron spectroscopy to determine its band gap and valence band offset. Conducting AFM shows a good correlation between topography and current mapping, pointing to direct tunneling conduction. Long channels MOSFETs with low equivalent oxide thickness (EOT) were fabricated and their channel mobility measured. Mobility enhancement can be achieved by post processing annealing in various gases but at the cost of interfacial regrowth. An alternative approach to increase mobility without changing EOT is by electrically stressing the gate dielectric at ~150 o C.

Highly scaled FinFET SRAM cells, of area down to 0.128μm 2 , were fabricated using high-κ dielectric and a single metal gate to demonstrate cell size scalability and to investigate V t variability for the 32 nm node and beyond. A single-sided ion implantation (I/I) scheme was proposed to reduce V t variation of Fin-FETs in a SRAM cell, where resist shadowing is a great issue. In the 0.187μm 2 cell, at V d = 0.6 V, a static noise margin (SNM) of 95 mV was obtained and stable read/write operations were verified from N-curve measurements. σV t of transistors in 0.187μm 2 cells was measured with and without channel doping and the result was summarized in the Pelgrom plot. With the 22 nm node design rule, FinFET SRAM cell layouts were compared against planar-FET SRAM cell layouts. An un-doped FinFET SRAM cell was simulated to have significant advantage in read/write margin over a planar-FET SRAM cell, which would have higher σV t mainly caused by heavy doping into the channel region.

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