Investigation of FinFET Devices for 32nm Technologies and Beyond

Shang, Huiling; Chang, Leland; Wang, X.; Rooks, M. J.; Zhang, Y.; To, B.; Babich, Katherina; Totir, George G.; Sun, Y.; Kiewra, E.; Ieong, M.; Haensch, Wilfried

doi:10.1109/vlsit.2006.1705213

Cited by 39 publications

(15 citation statements)

References 1 publication

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“…In this work, a conservative source/drain (S/D) contact scheme is assumed, in which large landing pads are used. Elimination of the S/D landing pads, e.g., by using local interconnects, would improve the FinFET layout efficiency but at the cost of increased parasitic capacitance [36].…”

Section: B Finfet Sram Cell Designs 1) Conventional Double-gated (Dgmentioning

confidence: 99%

SRAM Read/Write Margin Enhancements Using FinFETs

Carlson

Guo

Balasubramanian

et al. 2010

IEEE Trans. VLSI Syst.

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Abstract-Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM performance and yield enhancement through independent gating. The enhancements to read/write margins and yield are investigated in detail for two cell designs employing independently gated FinFETs. It is shown that FinFET-based 6-T SRAM cells designed with pass-gate feedback (PGFB) achieve significant improvements in the cell read stability without area penalty. The write-ability of the cell can be improved through the use of pull-up write gating (PUWG) with a separate write word line (WWL). The benefits of these two approaches are complementary and additive, allowing for simultaneous read and write yield enhancements when the PGFB and PUWG designs are used in combination.

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Section: B Finfet Sram Cell Designs 1) Conventional Double-gated (Dgmentioning

confidence: 99%

SRAM Read/Write Margin Enhancements Using FinFETs

Carlson

Guo

Balasubramanian

et al. 2010

IEEE Trans. VLSI Syst.

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“…Fully depleted SOI (FDSOI with undoped body) FINFETs (double gate) with high-κ/metal gates are fabricated using a sidewall image transfer flow [2] with tight fin pitch (52 nm) on [100] Si substrates, so that the channel transport orientation is [110]. A transmission electron micrograph (TEM) of an individual fin device is shown in the inset of Fig.…”

Section: Theory and Experimentsmentioning

confidence: 99%

Extraction of Effective Oxide Thickness for SOI FINFETs With High- $\kappa$/Metal Gates Using the Body Effect

Paul¹,

Yeh

Maitra

et al. 2010

IEEE Electron Device Lett.

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A methodology based on the transistor body effect is used to monitor inversion oxide thicknesses (T inv 's) in high-κ/metal-gate undoped ultrathin-body short-channel SOI FINFETs. The extracted T inv 's are benchmarked to independent capacitance-voltage (C-V ) measurements. For the first time, device simulation is introduced to understand the fundamental difference in T inv values extracted using the two techniques, which is driven by the inversion charge centroid at different bias conditions. Index Terms-Fully depleted SOI (FDSOI), FINFETs, inversion oxide thickness, ultrathin body.

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“…The feasibility of basic analog and digital circuits has already been demonstrated [3]. Technology issues such as large fin pitch, sidewall roughness and high parasitic resistances are still not fully solved, nevertheless there are promising approaches [4].…”

Section: Introductionmentioning

confidence: 99%

Analog design challenges and trade-offs using emerging materials and devices

Fulde

Mercha

Gustin

et al. 2007

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference

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Analog device figures-of-merit change significantly with the introduction of advanced materials and devices such as high-k or Multiple-Gate FETs. Measurements show enhanced intrinsic gain and matching behavior for MuGFETs which help to reduce area and power consumption in analog circuits. However, high-k degrades matching, flicker noise and VT stability. Measured device performance is used to simulate the impact of these trends on circuit design trade-offs. Migrating from SiON to HfO2 dielectric approximately doubles area and power consumption to keep matching and noise performance constant. Transient VT instabilities in the range of 10mV can degrade the resolution of analog-to-digital converters by more than one bit. The use of non-binary ADCs is proposed to overcome these issues.

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Investigation of FinFET Devices for 32nm Technologies and Beyond

Cited by 39 publications

References 1 publication

SRAM Read/Write Margin Enhancements Using FinFETs

SRAM Read/Write Margin Enhancements Using FinFETs

Extraction of Effective Oxide Thickness for SOI FINFETs With High- $\kappa$/Metal Gates Using the Body Effect

Analog design challenges and trade-offs using emerging materials and devices

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