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The effort to design RF circuits in CMOS is motivated by low cost and significant capacity for on-chip integration. We discuss some of the challenges of implementing RF designs in CMOS focusing on those introduced by the changing properties of FETs as technology nodes scale and devices shrink. We present methods and tools using which designers can ease these challenges and reduce the risk of implementing RF circuits in CMOS.

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A 300-mm wafer-level three-dimensional integration (3DI) process using tungsten (W) through-silicon vias (TSVs) and hybrid Cu/adhesive wafer bonding is demonstrated. The W TSVs have fine pitch (5 μm), small critical dimension (1.5 μm), and high aspect ratio (17:1). A hybrid Cu/adhesive bonding approach, also called transfer-join (TJ) method, is used to interconnect the TSVs to a Cu BEOL in a bottom wafer. The process also features thinning of the top wafer to 20 μm and a Cu backside BEOL on the thinned top wafer. The electrical and physical properties of the TSVs and bonded interconnect are presented and show RLC values that satisfy both the power delivery and high-speed signaling requirements for high-performance 3D systems. Introduction3DI is a promising technology to further improve the performance of computational systems [1][2][3]. 3DI enables increased functions per physical die area, and can dramatically increase the available cache memory in multicore architectures. Previously, W TSVs for silicon carrier applications have been demonstrated with both high yield and reliability [4]. In addition, a hybrid metal/adhesive TJ process has been shown to be a highly reliable inter-chip connection process in multi-chip modules [5]. However, neither of these technologies has been demonstrated in a full integrated process on a 300-mm platform. In this paper, we utilize the combination of W TSVs and transfer-join assembly on 300-mm wafers, and demonstrate the functionality and robustness of this process.