A concept for a BiCMOS implementation of a RISC microprocessor CPU is proposed. It is based on a CMOS implementation without architectural changes to maintain software compatib~ty. The circuit paths are analyzed and the provisions for special functional units such as the cache, data path and internal memory are derived. A significant performance gain --about factor 2.5 --is achieved with a limited number of bipolar current switches. BiCMOS permits the performance of ECL versions at a substantially lower power budget and area consumption by combining CMOS technology for memory cell arrays and the bulk of logic circuits with ECL in time-critical paths.
A high performance BICMOS process denoted B5C for the realization of higb speed/higb density integrated circuits is presented. The main features of this process are L.0 micron minimnl feature size and a selfaligned bipolar transistor of L0 GHz cutoff frequeny and 50 ps minimal CML stage-delay time. Moreover bipolar transistors with 70V Early-voltage are available using one additional masking step. As a more complex performance-demonstrator n high speed 16k SRAM with 3.5ns adress access time is presented. Both delay times show, that B5C is one of the fastest BICMOS processes worldwide.
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