Merged CMOS/bipolar current switch logic (MCSL)

Heimsch, W.; Hoffmann, B.; Krebs, R.; Mullner, E.; Pfaffel, B.; Ziemann, K.

doi:10.1109/jssc.1989.572603

Cited by 31 publications

(2 citation statements)

References 3 publications

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“…SiGe BiCMOS technologies are now considered as mid-cost while they provide both high-speed Heterojuntion Bipolar Transistors (HBT) and CMOS transistors. Merged CMOS/Bipolar current switch logic (MCSL) has been suggested [6] in order to reduce the adder power consumption. The 3-levels series BiCMOS phase accumulator proposed in this paper consists of a ninebits ripple adder followed by a 9-bits register.…”

Section: B Bicmos Phase Accumulatormentioning

confidence: 99%

A 6-GHz Low-Power BiCMOS SiGe:C 0.25 $\mu$m Direct Digital Synthesizer

Thuries

Tournier

Cathelin

et al. 2008

IEEE Microw. Wireless Compon. Lett.

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A 6-GHz low power SiGe direct digital synthesizer (DDS) is reported. This paper discusses the BiCMOS design improvements used for the phase accumulator and the phase-toamplitude conversion in order to achieve higher speed operation and lower power consumption compared to existing DDS. The phase accumulator is based on a three-level BiCMOS logic, and the phase-to-amplitude conversion is completed through a bipolar differential pair. The circuit has been processed in a BiCMOS SiGe:C 0.25 µm technology. The power consumption is 308 mW and it operates from a 2.8 V supply. The chip core area is 1 mm 2 .

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Section: B Bicmos Phase Accumulatormentioning

confidence: 99%

A 6-GHz Low-Power BiCMOS SiGe:C 0.25 $\mu$m Direct Digital Synthesizer

Thuries

Tournier

Cathelin

et al. 2008

IEEE Microw. Wireless Compon. Lett.

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“…Since ECL-like reduced swing operation is the key to the high speed in these macros, an ECL+CMOS type BiCMOS [3,7,8,9] seems promising. In the ECL+CMOS type BiCMOS, the communication between ECL and CMOS is important.…”

Section: Bicmos Macro Examdle and Future Trendmentioning

confidence: 99%

High-speed/high-density logic circuit design

Sakurai

1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers

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Problems and possible solutions to implement high-speed logic VLSI's with advanced CMOS I BiCMOS technology are discussed. The technology trend is summarized first in conjunction with its impact on the circuit designs. The paper covers BiCMOS circuit designs and other basic high-speed circuit techniques including gate sizing, dynamic I reduced swing circuits, interconnect I clock delay, and on-chip memory. These items are discussed with possible scaling effects. Future highspeed design should cope with 1 o w -V~~ related problems including threshold voltage scaling, interconnection delay problems including clock distribution problems, power and noise. These constraints get severer as scaling advances.

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