High-speed/high-density logic circuit design

Abstract

Problems and possible solutions to implement high-speed logic VLSI's with advanced CMOS I BiCMOS technology are discussed. The technology trend is summarized first in conjunction with its impact on the circuit designs. The paper covers BiCMOS circuit designs and other basic high-speed circuit techniques including gate sizing, dynamic I reduced swing circuits, interconnect I clock delay, and on-chip memory. These items are discussed with possible scaling effects. Future highspeed design should cope with 1 o w -V~~ related problems including threshold voltage scaling, interconnection delay problems including clock distribution problems, power and noise. These constraints get severer as scaling advances.

Electromigration-aware design

“…Table I shows the simulation results. For the resistance we have used a simple approximation in which the resistance is inversely proportional to the cross sectional area, while for capacitance we have used formulas by Sakurai [8,9] and Chern [3]. As can be seen from the table, using "fat" wires results in a 27% reduction in RC product compared to the regular configuration; the use of routing vias provides an additional 15% for a total of 42% reduction in RC delay.…”