A 6-GHz Low-Power BiCMOS SiGe:C 0.25 $\mu$m Direct Digital Synthesizer

Thuries, S.; Tournier, E.; Cathelin, Andreia; Godet, Sylvain; Graffeuil, J.

doi:10.1109/lmwc.2007.911994

Cited by 28 publications

(11 citation statements)

References 10 publications

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“…Although the attempts to replace the traditional ROM-based designs [10]- [16], including CORDIC [15]- [19], polynomials, and quadraticbased designs [20]- [23] have been suggested, they suffer from high design complexity and still power overhead. Then, another approaches for developing analog mapper to replace the digital mapper have been proposed [24]- [26]. In this new topology using the analog mapping block as illustrated in FIGURE 2 (b), the P2A conversion is performed through the post-DAC analog method, resulting in a significant power reduction.…”

Section: Design Of the Low Power Ddfs A Conventional Ddfs Methodmentioning

confidence: 99%

Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer

et al. 2020

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Due to the advantages of fast frequency shifting, continuous phase shifting, fine frequency resolution, large bandwidth, and excellent spectral purity, the direct digital frequency synthesis (DDFS) technique is attracting more attention than ever before. Although the DDFS suffer from high power consumption, recent researches on the development of the low power DDFS (LP-DDFS) increases the feasibility of applying the DDFS to portable devices. To further accelerate the use of LP-DDFS, a new LP-DDFS design to significantly improve power efficiency is proposed and analyzed in this paper. In the new design, the dominant spur by truncation errors causing performance degradation has been also thoroughly considered. Since the existing dithering techniques for the truncation error problems can cause the additional performance degradation due to the side effects such as frequency offset and SNDR deterioration, an enhanced dithering technique is also proposed in this paper. The proposed technique includes a frequency compensation circuit and thus minimizes the truncation errors in the LP-DDFS with the minimal additional power consumption and SNDR degradation. Both theoretical and experimental analysis are conducted to verify the proposed design, where a prototype chip is fabricated and measured. INDEX TERMS Direct digital frequency synthesizer (DDFS/DDS), dithering scheme, high spuriousfree dynamic range (SFDR), low power design, Phase accumulator (PACC), pseudo-random binary sequence (PRBS).

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Section: Design Of the Low Power Ddfs A Conventional Ddfs Methodmentioning

confidence: 99%

Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer

et al. 2020

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“…To overcome this, a trade-off on the diversity of waveforms that can be generated had to be made in order to suppress the ROM. Thus, high-speed DDS are focused on sine wave generation [3], [4], [5] and are then able to reach only a few hundred mW on low-cost Silicon-Germanium technologies [6], [7].…”

Section: Introductionmentioning

confidence: 99%

A both Gaussian and sinusoidal phase-to-amplitude converter for low-power ultra-high-speed direct digital synthesizers

Borr

Juyon

Tournier

2011

2011 IEEE 9th International New Circuits and Systems Conference

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To cite this version:Teddy Borr, Julien Juyon, Éric Tournier. A both Gaussian and sinusoidal phase-to-amplitude converter for low-power ultra-high-speed direct digital synthesizers. NEWCAS, Jun 2011, Bordeaux, Abstract-This paper introduces a new bipolar differential pair topology for both gaussian and sinusoidal signal shaping, to be used as a phase-to-amplitude converter alternative in lowpower ultra-high-speed DDS. A DDS using this converter, with a 9-bit frequency resolution and an 8-bit amplitude resolution has been designed in a 0.13 µm SiGe BiCMOS technology, with f t /f max of 200/250 GHz, and simulated up to a 20 GHz operating clock frequency. It consumes 585 mW under a 2.8 V power supply. Simulated triangle shape allows an optimal SFDR of −44.5 dBc in sinus mode and a SLRR of −43.5 dBc in gaussian mode.

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“…Integrated direct digital synthesizer (DDS) circuits with clock frequencies up to 32 GHz have been presented in the past using InP [1], [2] or SiGe technologies [3]- [5]. Different approaches for the triangle-sine-wave conversion have been shown including the nonlinear-DAC [2], [5] and the differential pair [3], [4] architecture.…”

Section: Introductionmentioning

confidence: 99%

“…Different approaches for the triangle-sine-wave conversion have been shown including the nonlinear-DAC [2], [5] and the differential pair [3], [4] architecture. The choice of architecture has a huge impact on system design; the differential pair based approach has been shown to offer up to seven times lower power consumption, lowest chip area, and higher clock frequency than other circuits in comparable technology [4].…”

Section: Introductionmentioning

confidence: 99%

Temperature calibration of a differential pair based direct digital synthesizer through subsampling spectral analysis

Laemmle

Wagner

Jaeger³

et al. 2010

2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

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The temperature behavior of a high speed direct digital synthesizer with a maximum clock frequency of 16.8 GHz and a power consumption of 488 mW at room temperature is investigated. The DDS has been manufactured in a 200-GHz ft SiGe bipolar technology and occupies a chip area of 1.15 mm 2 . A subsampling approach is introduced to analyze the output spectrum of the DDS. A calibration is performed over temperature to improve the spectral performance of the DDS. The calibration is based on a two point measurement and the use of a look-up table. After calibration, the third harmonic is below 53 dBc and a narrow band SFDR is nearly constant at 38 dBc.

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A 6-GHz Low-Power BiCMOS SiGe:C 0.25 $\mu$m Direct Digital Synthesizer

Cited by 28 publications

References 10 publications

Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer

Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer

A both Gaussian and sinusoidal phase-to-amplitude converter for low-power ultra-high-speed direct digital synthesizers

Temperature calibration of a differential pair based direct digital synthesizer through subsampling spectral analysis

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