Merged CMOS/bipolar current switch logic

Heimsch, W.; Hoffmann, B.; Krebs, R.; Muellner, E.; Pfaeffel, B.; Ziemann, K.

doi:10.1109/isscc.1989.48199

Cited by 13 publications

(2 citation statements)

References 2 publications

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“…The three-levels series BiCMOS adder proposed in this paper consists in two blocks, the first for the sum and the second for the carry. [5], [6] show examples of mixing MOS and bipolar transistors. But we can notice a current bias source at the lower level and some input transistors at a second level.…”

Section: Multi-level Bicmos Ecl-type Full-addermentioning

confidence: 99%

A 3-bits DDS Oriented Low Power Consumption 15 GHz Phase Accumulator in a 0.25 μm BiCMOS SiGe:C Technology

Thuries

Tournier

Graffeuil

2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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A 3 bits -0.25 µm BiCMOS SiGe:C accumulator operating up to 15 GHz clock frequency is presented. It is based on a high-speed and low-power three-levels BiCMOS logic which is used to implement the 1 bit full-adder and the D-flip-flop latch-up register. With this technique, the dissipated power is reduced by 30% over the usual four-levels series logic. The circuit integrates 203 (without buffers, 230 with) transistors and dissipates 67 mW (without buffers, 119 with) from a 2.7 V supply.

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Section: Multi-level Bicmos Ecl-type Full-addermentioning

confidence: 99%

A 3-bits DDS Oriented Low Power Consumption 15 GHz Phase Accumulator in a 0.25 μm BiCMOS SiGe:C Technology

Thuries

Tournier

Graffeuil

2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

View full text Add to dashboard Cite

show abstract

“…At Siemens so far emphasis was put mainly on basic circuitry and on the development of innovative circuit schemes like the "merged CMOS/bipolar logic" (MCSL) (16,17). Using this circuit technique adder macros were realized (Fig.…”

Section: Demonstratorsmentioning

confidence: 99%