A 3-bits DDS Oriented Low Power Consumption 15 GHz Phase Accumulator in a 0.25 μm BiCMOS SiGe:C Technology

Abstract

A 3 bits -0.25 µm BiCMOS SiGe:C accumulator operating up to 15 GHz clock frequency is presented. It is based on a high-speed and low-power three-levels BiCMOS logic which is used to implement the 1 bit full-adder and the D-flip-flop latch-up register. With this technique, the dissipated power is reduced by 30% over the usual four-levels series logic. The circuit integrates 203 (without buffers, 230 with) transistors and dissipates 67 mW (without buffers, 119 with) from a 2.7 V supply.

A high resolution DDFS design on VHDL using bipartite table method

“…1. In DDFS designs, many improvements are revealed to achieve better spectral performance [8], lower power dissipation [9], [10], higher frequency resolution [11] and smaller required area [12]- [14]. This paper presents a high resolution, LUT based DDFS design on VHDL.…”