A 3.8-ns 16 K BiCMOS SRAM

BICMOS: From Dream to Reality

“…The SRAM shows an access-time of 3.8ns (shown in Fig. 5), a power dissipation of 2W and an area-consumption of 23 mm 2 (14,19). The high speed macros of the ECl gate array have stage-delay times down to around SOps for double ended stages.…”