BiCMOS approach for a RISC microprocessor

Abstract

A concept for a BiCMOS implementation of a RISC microprocessor CPU is proposed. It is based on a CMOS implementation without architectural changes to maintain software compatib~ty. The circuit paths are analyzed and the provisions for special functional units such as the cache, data path and internal memory are derived. A significant performance gain --about factor 2.5 --is achieved with a limited number of bipolar current switches. BiCMOS permits the performance of ECL versions at a substantially lower power budget and area consumption by combining CMOS technology for memory cell arrays and the bulk of logic circuits with ECL in time-critical paths.