IntroductionHfO 2 gate dielectrics are considered to be the most promising high-k dielectrics to meet the future ULSI application, due to its high dielectric constant and excellent thermal stability [1][2][3]. Besides, as MOS devices continue to be scaled down, the low supply voltage is desirable to minimize the power consumption. Dynamic threshold voltage (DT) MOSFET has been extensively studied [4], being attractive for lower power supply voltage applications. In addition, the CESL stressor [5][6] has been used to improve mobility in CMOS technology. However, the combination of DT and CESL nMOS with high-k in CMOS technology has yet to be proposed. In this work, the mechanism and reliability of DT-CESL-HfO 2 nMOSFETs were deeply investigated. Device PreparationA 0.35-μm process was used with local-oxidation-of-silicon (LOCOS) isolation. After standard RCA cleaning, the HfO 2 thin film with 1.6 nm (CET) was deposited on Si wafer. Then, α-Si (deposition at 550 o C,) of thickness 50 nm was deposited in order to get the local tensile strain n-channel [6], and the final poly-gate thickness was 150 nm. After the S/D formation, a low pressure chemical vapor deposition (LPCVD) 50 nm silicon nitride (CESL) was directly deposited on the transistor at 780 o C and followed by a 200 nm PE-SiO 2 deposition. After contact alignment, the PE-oxide and SiN layer on the S/D regions were etched in the same system. After these processes, a four-level metallization (Ti-TiN-Al-TiN) was carried out in the PVD system for the contact. Figure 1 shows the schematic diagram of DT-CESL-nMOS transistor with HfO 2 gate dielectric. As shown in Fig. 1, the poly-Si gate is directly connected to the p-well region. Figure 2 shows the I D -V D characteristics of the CESL strained HfO 2 nMOSFETs at normal and DT biasing, where the device channel length and width were 0.5 and 10 μm, respectively. The drain current of DT mode showed 133% increase over the normal mode for the CESL-device at V D = V G = V B = 0.7 V, as shown in Fig. 2. This large increase can be attributed to the body bias effect. For the DT mode, the device is in on-state. On the contrary, the device with normal operation is operated in depletion region. Figure 3 demonstrated the transconductance (g m ) of CESL-devices with different channel length, at DT and normal biasing, respectively. The g m under DT mode is larger than that under the normal mode. The enhancement of g m , compared to the normal operation mode, was increased, with channel length decreasing as shown in this figure. A roughly 138 % increase can be observed for the 0.35μm CESL-device at DT biasing, by comparison with the normal mode. On the other hand, the increase of g m was only about 40 % for the 1μm CESL-device. These results imply that the increase of electron mobility is different in different channel length for the DT-CESL-MOS with HfO 2 gate dielectrics. In addition, this performance enhancement of the DT-CESL-nMOS can be speculated to the inversion charge density increase at DT biasing, as shown in Fig. 4. T...
For the first time, the compact analytical expressions of zero-temperature-coefficient (ZTC) point modeling of DTMOS transistor are successfully presented in detail. Newly analytical formulations are developed for both linear and saturation regions of DTMOS transistor operation that ensure the drain current to be temperature independent for the optimal gate voltage. The maximum error of 0.87% and 2.35% in the linear and saturation regions confirms good agreement between our DTMOS ZTC point model and the experimental data, respectively. Compared to traditional MOSFET, the lower V g (ZTC) with higher overdrive current of DTMOS improves the speed and efficiency of ICs for the low power consumption requirement in green CMOS technology.
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