Asynchronous circuits already have shown their benefits. The main drawback is the lack of powerful CAD and layout generation tools limiting the widespread use of the asynchronous methodology. QDI asynchronous circuits are known as a powerful category of asynchronous circuits targeting performance and power driven design. In this paper we addressed standard cell implementation of the template based QDI circuits utilizing standard layout generation tools. This is achieved by analyzing and removing outer cell isochronic fork constraint which is the main timing constraints limiting the standard layout generation. The isochronic fork free final netlist has 10-20% area overhead in average which is the cost of facilitating the use of standard CAD tools.
U i s poper introduces an imrovririve lrig/i-ievel method to estimate aicrgy consumption of a well hiown farnib of aqnchronous circuitr ut CSP Iewl. therefore renloviug the need for per$orniing time cowming SPICE simulatiorr. Oiu method is based 011 lrmsition count and M p s die PCHBJ'CFB !emplate bosed (201 aqmchronous circuit designers io huw an early cstinmtion of power with ihe acnrracy of mum than 80%. This evlimation. obtained from commnercial fumtiord simlutors, timy lead 10 power optiniiiution oflhe circuit iri high levels of desigti.
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