A novel clock generation scheme for globally asynchronous locally synchronous systems

Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating

“…This prevents metastablity during asynchronous communication. The Den signal is activated on the falling edge of clock because using left edge of the clock leaves the controller of the LS module unchanged [8]. After data communication, the clock will be released.…”

“…These sequences of events are shown in figure 2. The STG diagrams of pausible clock based GALS port controllers could be found in [4] [8]. The circuit in figure 3 is a typical implementation of pausible clock generator [4].…”

“…If incoming data arrives too close to sampling clock edge, either the clock edge or data transfer is shifted to a later point in time [4]. It must be also taken into consideration that when the clock generator stops the clock, there may be still clock edges in the buffer tree and therefore, the delay of the chain must be longer than the delay of clock buffer and tree [8]. Also the delay of the port controller (T pc ) and delay of the OR gate (T or ) has much effect on LS modules frequency.…”