FPGA Implementation of Gated Clock based Globally Asynchronous Locally Synchronous Wrapper Circuits

Amini, Esmail; Najibi, Mehrdad; Jeddi, Zahra; Pedram, Hossein

doi:10.1109/isscs.2007.4292699

Cited by 6 publications

(4 citation statements)

References 3 publications

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“…[7]- [9] proposed an interface circuit based on handshake signals to transfer data between local synchronous modules in GALS systems. In [7], an interface circuit is designed using a pausible clock [17].…”

Section: Related Workmentioning

confidence: 99%

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A Design Support Tool Set for Interface Circuits Between Synchronous and Asynchronous Modules

Semba

Saitō

2023

IEEE Access

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In this paper, we propose a design support tool set for interface circuits between synchronous and asynchronous modules. To facilitate the design of interface circuits between synchronous and asynchronous modules, the proposed tool set generates interface circuits and design constraints based on a predefined communication scheme. In addition, the proposed tool set performs timing verification and delay adjustment to guarantee the operations of the generated interface circuits. In the experiment, we evaluated the latency and overhead of the generated interface circuits. The latency and handshake overhead of the interface circuits generated by the proposed tool set depend on the cycle time of the receiver module. In addition, we designed a system which consists of a synchronous RISC-V processor and an asynchronous multilayer perceptron (MLP) circuit using the proposed tool set. The energy consumption of the system was reduced by 34.0% compared with a system which uses a synchronous MLP circuit.INDEX TERMS interface circuits, asynchronous circuits, design automation, low power I. INTRODUCTION

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Section: Related Workmentioning

confidence: 99%

“…The pausible clock is based on an on-chip ring oscillator to pause the clock signal. In [8] and [9], to reduce the power consumption of interface circuits, clock gating is applied to interface circuits. In [7]- [9], controllers of the interface circuits are synthesized by specific tools such as 3D Tool [18] and Petrify [19].…”

Section: Related Workmentioning

confidence: 99%

A Design Support Tool Set for Interface Circuits Between Synchronous and Asynchronous Modules

Semba

Saitō

2023

IEEE Access

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“…The communication ports are asynchronous controllers, and subject to its inherent problems. Jia [16] shows the advantages of implementing GALS in FPGA, highlighting the elimination of the clock skew problem. On the other hand, the biggest problem of GALS approach for FPGAs is the asynchronous communication, which must be performed by the controllers (ports) [17][18][19][20][21][22][23], showing some kind of essential-hazard or not satisfying the isochronic fork concepts.…”

Section: Input Port Controllermentioning

confidence: 99%

Design Of An Improved And Robust Asynchronous Wrapper (Aw) For FPGA Applications

Oliveira¹,

Faria²,

Lussari³

2020

JICS

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Contemporary digital systems must be based on the “System-on-Chip – SoC” concept. An interesting style for SoC design is the GALS paradigm (Globally Asynchronous, Locally Synchronous), which can be used to implement circuits in FPGAs (Field Programmable Gate Arrays). However the implementation of asynchronous interfaces (asynchronous wrapper – AW) constitutes a major drawback for this kind of devices. Although there is a typical AW design style, which is based on asynchronous controllers providing communication between modules (called ports), port controllers are subject to essentialhazard when implemented in FPGAs. In this context, this paper proposes a new asynchronous GALS wrapper architecture, suitable for implementations in any kind of FPGAs. The proposed port controllers showed to be essential-hazard-free, not needing any special cares in implementation concerning to LUTs choice. Additional advantages of the proposed architecture are: total autonomy that synchronous modules achieve when interacting with the asynchronous wrapper; the ports can be synthesized in the direct mapping style (so without knowledge of asynchronous logic synthesis); and the ports interact with environment in Ib/Ob Mode, not needing a timing analysis. Simulation results show the applicability of the proposed architecture and lead to its practical implementations in FPGAs.

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“…A notable exception is Ref. 11 where, in the context of a gated clock implementation for an asynchronous GALS wrapper, a synchronizer design is proposed that more or less successfully tries to mask out intermediate voltage levels. This synchronizer, however, is not generic; it handles one-sided (down-) transitions of the data only, for up-transitions the synchronizer would fail and synchrony between data and clock is assumed in the given context.…”

Section: Related Workmentioning

confidence: 99%

On the Appropriate Handling of Metastable Voltages in FPGAs

Polzer

Najvirt

Beck

et al. 2015

J CIRCUIT SYST COMP

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The signi¯cant process, voltage and temperature (PVT) variations seen with modern technologies make strictly synchronous design ine±cient. Asynchronous design with its°exible timing is a promising alternative, but prototyping is di±cult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in principle but cannot safely handle metastability issues that are inevitable even at some interfaces in asynchronous designs. In this paper, we propose reliable implementations of the fundamental function blocks required to safely convert potential intermediate voltage levels that result from metastability into late transitions that can be reliably handled in the asynchronous domain. These are high-and low-threshold bu®ers as well as a Schmitt-trigger. We give elaborate background analysis for the proposed circuits and also present the associated routing constraints to make the Schmitt-trigger circuit work properly in spite of the uncertain routing within FPGAs. Furthermore, we propose a procedure for an \in situ reliability assessment" of the speci¯c Schmitt-trigger element under consideration, which also applies to metastability containment with high-or low-threshold bu®ers only. Our proof of concept is based on experimental results for both Xilinx and Altera FPGA platforms.

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FPGA Implementation of Gated Clock based Globally Asynchronous Locally Synchronous Wrapper Circuits

Cited by 6 publications

References 3 publications

A Design Support Tool Set for Interface Circuits Between Synchronous and Asynchronous Modules

A Design Support Tool Set for Interface Circuits Between Synchronous and Asynchronous Modules

Design Of An Improved And Robust Asynchronous Wrapper (Aw) For FPGA Applications

On the Appropriate Handling of Metastable Voltages in FPGAs

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