Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs

Najibi, Mehrdad; Saleh, K.; Naderi, M.; Pedram, Hossein; Sedighi, Mehdi

doi:10.1109/rsp.2005.41

Cited by 15 publications

(8 citation statements)

References 11 publications

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“…Из-за этого стоимость ошибки проектировщика многократно возросла за последнее время. В связи с этим среди компаний, имеющих отношение к микроэлектронной области, возник повышенный интерес к использованию ПЛИС для прототипирования разрабатываемых устройств [4,5]. Другим фактором, объясняющим популярность ПЛИС, является то, что при производстве схем небольшими партиями стоимость единицы продукции получается довольно высокой.…”

Section: Taking Into Account the Features Of Various Technologies In unclassified

Logic Resynthesis Methods for Layout Design of Microelectronic Circuits

Vasilyev¹,

Frolova²,

Иванова³

et al. 2020

IZVESTIYA SFedU. ENGINEERING SCIENCES

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Section: Taking Into Account the Features Of Various Technologies In unclassified

Logic Resynthesis Methods for Layout Design of Microelectronic Circuits

Vasilyev¹,

Frolova²,

Иванова³

et al. 2020

IZVESTIYA SFedU. ENGINEERING SCIENCES

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“…On the other hand, the term GALS was first used by Chapiro in [10], having been successfully used in many implementations, including FPGAs [15] and ASIC (Application Specific Integrated Circuit) [13,14]. A GALS system consists of many synchronous functional modules (that may be IPs), which carries its own individual clock signals and communicate to each On the other hand, the ports proposed in [21][22][23] were specified in XBM (Extended Burst-Mode) and BM (Burst-Mode).…”

Section: Theorectical Backgroundmentioning

confidence: 99%

Design Of An Improved And Robust Asynchronous Wrapper (Aw) For FPGA Applications

Oliveira¹,

Faria²,

Lussari³

2020

JICS

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Contemporary digital systems must be based on the “System-on-Chip – SoC” concept. An interesting style for SoC design is the GALS paradigm (Globally Asynchronous, Locally Synchronous), which can be used to implement circuits in FPGAs (Field Programmable Gate Arrays). However the implementation of asynchronous interfaces (asynchronous wrapper – AW) constitutes a major drawback for this kind of devices. Although there is a typical AW design style, which is based on asynchronous controllers providing communication between modules (called ports), port controllers are subject to essentialhazard when implemented in FPGAs. In this context, this paper proposes a new asynchronous GALS wrapper architecture, suitable for implementations in any kind of FPGAs. The proposed port controllers showed to be essential-hazard-free, not needing any special cares in implementation concerning to LUTs choice. Additional advantages of the proposed architecture are: total autonomy that synchronous modules achieve when interacting with the asynchronous wrapper; the ports can be synthesized in the direct mapping style (so without knowledge of asynchronous logic synthesis); and the ports interact with environment in Ib/Ob Mode, not needing a timing analysis. Simulation results show the applicability of the proposed architecture and lead to its practical implementations in FPGAs.

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“…There have been some recent efforts to prototype asynchronous circuits on both commercial [23], [24] and academic FPGAs [25]. There are two reasons as to why off-the-shelf FPGAs are not fit to BGWD controllers [23], [26] and [27]:…”

Section: Fpga Implementation Of B Gwd Controllersmentioning

confidence: 99%

Synthesis of Asynchronous Controllers on FPGA from Generalized Multi-Burst Graph Specification

Oliveira¹,

Ferreira²,

Romano³

2013

MSSE

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On pro mising area applicat ion of asynchronous is in Heterogeneous Systems (synchronous and asynchronous modules mixed). Asynchronous controllers are quite used in heterogeneous systems. The specificat ion of theses controllers requires two types of signals: level sensitive signals that are used as conditionals and transition sensitive signals. Another requirement is to describe concurrency between inputs/outputs. The Multi-Burst Graph (M BG) specification allows to describing these controllers in a co mpact form and it is familiar to designers of digital circu its. This paper proposes a generalization in the M BG specificat ion to increase the ability to describe the interaction between inputs/ outputs, i.e. increase the concurrency between them. Th is paper also proposes a method that starts fro m Generalized MBG specification and imp lements its hazard-free controllers on FPGAs. These devices have been mainly used for design of synchronous controllers. However, it is difficult to design asynchronous controllers on FPGAs, because the circuit may suffer fro m hazard problems. The method proposed implements this class of asynchronous controllers on FPGAs which are based on Look-Up Table (LUT) architectures. By doing this, the asynchronous circuits besides their intrinsic advantages over synchronous ones may also take advantage of integration, lower costs and short-time design associated with FPGA designs.

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Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs

Cited by 15 publications

References 11 publications

Logic Resynthesis Methods for Layout Design of Microelectronic Circuits

Logic Resynthesis Methods for Layout Design of Microelectronic Circuits

Design Of An Improved And Robust Asynchronous Wrapper (Aw) For FPGA Applications

Synthesis of Asynchronous Controllers on FPGA from Generalized Multi-Burst Graph Specification

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