NAND flash offers a range of compelling benefits that will keep attracting mobile and enterprise application developers as engineers tackle the hard problems of scaling the technology to sub-20 nm.S ince NAND flash entered the market in 1987, its relatively low cost, compact size, quiet operation, speed, and ruggedness have made it a popular choice for mobile platforms such as smartphones and tablets, and it is replacing hard drives in many client and enterprise applications.In recent years, developers have successfully scaled 2D NAND flash to sub-20-nm technology, but further 2D NAND scalability will be a considerable challenge. Although new alternatives, such as 3D resistive RAM (ReRAM), are aiming to replace 2D NAND flash, NAND's entrenched position among nonvolatile storage options and the attractiveness of its low power consumption will make flash technology difficult to unseat. In enterprise storage, for example, flash solid-state drive (SSD) architectures are already leveraging massive parallelism to deliver high I/O operations per second for less power and cost than any currently available and practical technology.With these strong advantages, NAND can potentially supplant a portion of the dynamic RAM (DRAM) market, 1 and we expect future computing platforms to maximize NAND flash use in mobile, enterprise, and client product designs. Indeed, Gartner has forecast that units in all applications will triple over the next five years, with an average fourfold to fivefold capacity increase in SSDs over the same period. 2 The widespread adoption of flash will drive deeper cost reductions, which manufacturers will realize through increased scaling. As NAND flash devices scale down, application-specific systems management must maintain product reliability while continuing to address reduced endurance.Maintaining the reliability of NAND flash at 19 nm and beyond will also require breakthrough memory and system algorithms. Many efforts are in progress on more innovations in memory architecture, reliability, power, and high-speed I/O interfaces. Another body of work is focusing on the system design challenges of scaling 2D NAND flash, offering 3D NAND and other novel technologies as possible solutions.
ArchitecturAl improvementsFor many years, half-bit-line (HBL), or shielded bit-line, architecture was the conventional NAND architecture in which, as Figure 1 shows, the system reads or writes only half the cells at a time to the word line. In 2008, SanDisk introduced all-bit-line (ABL) architecture, 3 which uses a current-sensing scheme to connect each bit line to the sensing amplifier and a set of data latches.ABL was a considerable improvement over HBL. In addition to doubling read and write throughput, ABL architecture has intrinsically better reliability. In HBL architecture, reading or programming stresses the same word line twice with high voltages; in ABL architecture, writing the same number of cells stresses the word line only once. The doubled high-voltage stress during program and read operations worsens m...
