A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate

Li, Yan; Lee, Seungpil; Fong, Y.; Pan, Feng; Kuo, Tien-Chien; Park, Jong-Min; Samaddar, Tapan; Nguyen, Hao; Mui, Man; Htoo, Khin; Kamei, Takeshi; Higashitani, M.; Yero, E.; Kwon, Gyuwan; Kliza, P.; Wan, Ji; Kaneko, Tetsuya; Maejima, H.; Shiga, H.; Hamada, Makoto; Fujita, Norihiro; Kanebako, K.; Tam, Eugene; Koh, A.; Lu, Iris M.; Kuo, C. P.; Pham, T.; Huynh, Jonathan; Nguyen, Qui; Chibvongodze, Hardwell; Watanabe, Mitsuyuki; Oowada, K.; Grishma, Shah; Woo, B.J.; Ray, G. P.; Chan, Jennifer; Lan, J.; Patrick, Hong; Peng, Liping; Das, D.; Ghosh, D.; Kalluru, V.; Kulkarni, S.; Cernea, Raul; Huynh, Sharon; Pantelakis, D.; Wang, Chiming; Quader, K.

doi:10.1109/jssc.2008.2007154

Cited by 52 publications

(20 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…All the memory-cell blocks share the bit lines and an on-chip page buffer that holds the data being programmed or fetched. Modern NAND Flash memories use either even/odd bit-line structure [19], [20] or all-bit-line structure [21], [22]. In the even/odd bit-line structure, even and odd bit lines are interleaved along each word line and are alternatively accessed.…”

Section: A Nand Flash Memory Basicsmentioning

confidence: 99%

“…The threshold voltage of an erased state tends to have a wide Gaussian-like distribution [24]. Hence, we model the threshold-voltage distribution of the erased state as (3) where and are the mean and standard deviation of the erased-state threshold-voltage distribution. For the other programmed states, as pointed out earlier, each memory cell is programmed using an iterative program-and-verify approach with a step voltage of .…”

Section: Cell-threshold-voltage Distribution Modelmentioning

confidence: 99%

See 1 more Smart Citation

Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory

Dong

Shu

Zhang

2010

IEEE Trans. Circuits Syst. I

130

112

View full text Add to dashboard Cite

With the appealing storage-density advantage, multilevel-per-cell (MLC) NAND Flash memory that stores more than 1 bit in each memory cell now largely dominates the global Flash memory market. However, due to the inherent smaller noise margin, the MLC NAND Flash memory is more subject to various device/circuit variability and noise, particularly as the industry is pushing the limit of technology scaling and a more aggressive use of MLC storage. Cell-to-cell interference has been well recognized as a major noise source responsible for raw-memory-storage reliability degradation. Leveraging the fact that cell-to-cell interference is a deterministic data-dependent process and can be mathematically described with a simple formula, we present two simple yet effective data-processing techniques that can well tolerate significant cell-to-cell interference at the system level. These two techniques essentially originate from two signal-processing techniques being widely used in digital communication systems to compensate communication-channel intersymbol interference. The effectiveness of these two techniques have been well demonstrated through computer simulations and analysis under an information theoretical framework, and the involved design tradeoffs are discussed in detail.

show abstract

Section: A Nand Flash Memory Basicsmentioning

confidence: 99%

Section: Cell-threshold-voltage Distribution Modelmentioning

confidence: 99%

Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory

Dong

Shu

Zhang

2010

IEEE Trans. Circuits Syst. I

130

112

View full text Add to dashboard Cite

show abstract

“…Nevertheless, a bigger will increase the width of each programmed level and hence reduce the noise margin between adjacent programmed levels, leading to data retention time degradation. Modern flash memory chips can support dynamic configuration of the programming speed vs. data retention time trade-off [3].…”

Section: Nand Flash Memory Programming Speed Vs Data Retention Time mentioning

confidence: 99%

“…Therefore, there is a fundamental trade-off between NAND flash memory programming speed and data retention time. This makes it possible to temporally boost memory programming speed at the cost of data retention time, which has already been used in latest commercial products [3]. The above discussion suggests an on-demand fast-write-and-rewrite design strategy: Whenever necessary, we temporally boost NAND flash memory programming speed to ensure the desired SSD response time.…”

Section: Introductionmentioning

confidence: 99%

OFWAR: Reducing SSD Response Time Using On-Demand Fast-Write-and-Rewrite

Zhang

2014

IEEE Trans. Comput.

View full text Add to dashboard Cite

This paper presents a cross-layer design strategy to reduce SSD response time and its variation. The key is to cohesively exploit system-level run-time data access workload variation and temporal locality and device-level NAND flash memory write latency versus data retention time trade-off. The basic idea is simple: once write intensity of the workload increases and begins to degrade SSD response time, we speed up memory programming at the penalty of shorter data retention time, and rewrite these short-lifetime data later, if necessary, when workload write intensity drops. A scheduling solution is developed to effectively implement this design strategy. Simulations over various workloads were carried out and the results demonstrate that the cross-layer design strategy can reduce the average SSD response time by up to 52.3%.

show abstract

“…On the other hand, multi-level per cell (MLC) technology enabling a memory cell to store more than 1 bit has been developed to increase the storage density of NAND flash memory. In current design practice, 2 bits per cell NAND flash memories are most prevailing in the market but possibilities of 3 and 4 bits per cell NAND flash memories are extensively explored [11], [17].…”

Section: Introductionmentioning

confidence: 99%

Concatenated BCH codes for NAND flash memories

Cho

2012

2012 IEEE International Conference on Communications (ICC)

View full text Add to dashboard Cite

In this work, we consider designing high-rate errorcontrol systems for storage devices using MLC NAND flash memories. Traditional systems designed with either a single BCH code or multiple short BCH codes may suffer from high decoding complexity or rate loss due to limited error-correcting capability, respectively. Aiming at achieving a stronger errorcorrecting capability with much reduced complexity, we propose an error-control system using a concatenation of short BCH codes with iterative decoding strategies. The performance of the proposed coding scheme is thoroughly analyzed and evaluated with computer simulations and a semi-analytic way at a target page-error rate, 10 −14 , which confirms our claims: the proposed coding scheme achieves good error-performance and complexity tradeoffs as compared to the traditional schemes and is very favorable for implementation.

show abstract

A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate

Cited by 52 publications

References 6 publications

Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory

Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory

OFWAR: Reducing SSD Response Time Using On-Demand Fast-Write-and-Rewrite

Concatenated BCH codes for NAND flash memories

Contact Info

Product

Resources

About