A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS

Trinh, Cuong; Shibata, Noboru; Nakano, Takuya; Ogawa, M.; Sato, Jumpei; Takeyama, Y.; Isobe, K.; Le, Binh; Moogat, Farookh; Nima, Mokhlesi; Kozakai, K.; Patrick, Hong; Kamei, Takeshi; Iwasa, K.; Nakai, J.; Shimizu, Tatsuo; Honma, Mareki; Sakai, Shigeki; Kawaai, T.; Hoshi, S.; Yuh, J.; Hsu, Cynthia; Tseng, Tsun-Ming; Li, J.; Hu, Jianghai; Liu, M.; Saifullah, Khalid; Chen, J.; Watanabe, Mitsuyuki; Lin, Hongwei; Yang, Jiangang; McKay, Kyle S.; Nguyen, Khanh; Pham, T.; Matsuda, Yoshihisa; Nakamura, K.; Kanebako, K.; Yoshikawa, Shinya; Igarashi, W.; Inoue, Akira; Takahashi, Tomoko; Komatsu, Y.; Suzuki, Chikashi; Kanazawa, K.; Higashitani, M.; Lee, Sungbae; Murai, Tadashi; Lan, J.; Huynh, Sharon; Murin, Mark; Shlick, Mark; Lasser, Marvin E.; Cernea, Raul; Mofidi, M.; Schuegraf, K.; Quader, K.

doi:10.1109/isscc.2009.4977400

Cited by 43 publications

(19 citation statements)

References 2 publications

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“…In practice, ML decoding complexity is usually prohibitive. In the next section, we move (4). Circles denote variable nodes (codeword symbols), and squares denote check nodes (parity-check equations).…”

Section: Maximum-likelihood Decodingmentioning

confidence: 99%

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Iterative Decoding of LDPC Codes Over the <inline-formula> <tex-math notation="LaTeX">$q$ </tex-math> </inline-formula>-Ary Partial Erasure Channel

Cohen

Cassuto

2016

IEEE Trans. Inform. Theory

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Abstract-In this paper, we develop a new channel model, which we name the q-ary partial erasure channel (QPEC). The QPEC has a q-ary input, and its output is either the input symbol or a set of M (2 ≤ M ≤ q) symbols, containing the input symbol. This channel serves as a generalization to the binary erasure channel, and mimics situations when a symbol output from the channel is known only partially; that is, the output symbol contains some ambiguity, but is not fully erased. This type of channel is motivated by non-volatile memory multi-level read channels. In such channels the readout is obtained by a sequence of current/voltage measurements, which may terminate with partial knowledge of the stored level. Our investigation is concentrated on the performance of low-density parity-check (LDPC) codes when used over this channel, thanks to their low decoding complexity using belief propagation. We provide the exact QPEC density-evolution equations that govern the decoding process, and suggest a cardinality-based approximation as a proxy. We then provide several bounds and approximations on the proxy density evolutions, and verify their tightness through numerical experiments. Finally, we provide tools for the practical design of LDPC codes for use over the QPEC.

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Section: Maximum-likelihood Decodingmentioning

confidence: 99%

“…The read process is usually performed by comparing the stored voltage level to certain threshold voltage levels. To scale storage density in NVMs, the number of levels per cell is continuously increased [3], [4]. As the number of levels increases, errors become more and more prevalent Copyright (c) 2014 IEEE.…”

Section: Introductionmentioning

confidence: 99%

Iterative Decoding of LDPC Codes Over the <inline-formula> <tex-math notation="LaTeX">$q$ </tex-math> </inline-formula>-Ary Partial Erasure Channel

Cohen

Cassuto

2016

IEEE Trans. Inform. Theory

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“…Since the measured threshold voltage distributions of recent flash memory products [2][3][4] are unimodal, the proposed verify level control criteria can be effectively applied to flash memories. In addition, the proposed verify level control criteria can be applied to other memories such as phase change memory (PCM) because the measured distributions of PCM in literature seem to be unimodal [26][27][28].…”

Section: Verify Level Control Criteria and Other Statistical Distribumentioning

confidence: 99%

“…To satisfy the market demand for lower cost per bit and higher density of nonvolatile memory, there are two approaches: (1) technology scaling, (2) multi-level cell (MLC) [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Verify level control criteria for multi-level cell flash memories and their applications

Kim

Kong

et al. 2012

EURASIP J. Adv. Signal Process.

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In M-bit/cell multi-level cell (MLC) flash memories, it is more difficult to guarantee the reliability of data as M increases. The reason is that an M-bit/cell MLC has 2 M states whereas a single-level cell (SLC) has only two states. Hence, compared to SLC, the margin of MLC is reduced, thereby making it sensitive to a number of degradation mechanisms such as cell-to-cell interference and charge leakage. In flash memories, distances between 2 M states can be controlled by adjusting verify levels during incremental step pulse programming (ISPP). For high data reliability, the control of verify levels in ISPP is important because the bit error rate (BER) will be affected significantly by verify levels. As M increases, the verify level control will be more important and complex. In this article, we investigate two verify level control criteria for MLC flash memories. The first criterion is to minimize the overall BER and the second criterion is to make page BERs equal. The choice between these criteria relates to flash memory architecture, bits per cell, reliability, and speed performance. Considering these factors, we will discuss the strategy of verify level control in the hybrid solid state drives (SSD) which are composed of flash memories with different number of bits per cell.

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“…Devices currently available use multiple levels and are referred to as multiple-level cell (MLC) flash. Four and eight levels are currently in use, and the number of levels will increase further to provide more storage capability [1] [2].…”

Section: Introductionmentioning

confidence: 99%

Soft Information for LDPC Decoding in Flash: Mutual-Information Optimized Quantization

Wang

Courtade

Shankar

et al. 2011

2011 IEEE Global Telecommunications Conference - GLOBECOM 2011

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Abstract-High-capacity NAND flash memory can achieve high density storage by using multi-level cells (MLC) to store more than one bit per cell. Although this larger storage capacity is certainly beneficial, the increased density also increases the raw bit error rate (BER), making powerful error correction coding necessary. Traditional flash memories employ simple algebraic codes, such as BCH codes, that can correct a fixed, specified number of errors. This paper investigates the application of lowdensity parity-check (LDPC) codes which are well known for their ability to approach capacity in the AWGN channel. We obtain soft information for the LDPC decoder by performing multiple cell reads with distinct word-line voltages. The values of the word-line voltages (also called reference voltages) are optimized by maximizing the mutual information between the input and output of the multiple-read channel. Our results show that using this soft information in the LDPC decoder provides a significant benefit and enables the LDPC code to outperform a BCH code with comparable rate and block length over a range of block error rates.

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A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS

Cited by 43 publications

References 2 publications

Iterative Decoding of LDPC Codes Over the <inline-formula> <tex-math notation="LaTeX">$q$ </tex-math> </inline-formula>-Ary Partial Erasure Channel

Iterative Decoding of LDPC Codes Over the <inline-formula> <tex-math notation="LaTeX">$q$ </tex-math> </inline-formula>-Ary Partial Erasure Channel

Verify level control criteria for multi-level cell flash memories and their applications

Soft Information for LDPC Decoding in Flash: Mutual-Information Optimized Quantization

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