Verify level control criteria for multi-level cell flash memories and their applications

Abstract

In M-bit/cell multi-level cell (MLC) flash memories, it is more difficult to guarantee the reliability of data as M increases. The reason is that an M-bit/cell MLC has 2 M states whereas a single-level cell (SLC) has only two states. Hence, compared to SLC, the margin of MLC is reduced, thereby making it sensitive to a number of degradation mechanisms such as cell-to-cell interference and charge leakage. In flash memories, distances between 2 M states can be controlled by adjusting verify levels during incremental step pulse programming (ISPP). For high data reliability, the control of verify levels in ISPP is important because the bit error rate (BER) will be affected significantly by verify levels. As M increases, the verify level control will be more important and complex. In this article, we investigate two verify level control criteria for MLC flash memories. The first criterion is to minimize the overall BER and the second criterion is to make page BERs equal. The choice between these criteria relates to flash memory architecture, bits per cell, reliability, and speed performance. Considering these factors, we will discuss the strategy of verify level control in the hybrid solid state drives (SSD) which are composed of flash memories with different number of bits per cell.

Reliability and hardware implementation of rank modulation flash memory

“…In the conventional flash, data stored in a cell will be faulty when Vth crosses the read threshold, usually set at the middle of the two distributions. Several schemes using dynamically adjusted read threshold have been proposed [7][8][9] for reducing read errors. But for RM, data will not be noisy as long as the relative order with the lower ranked cells is maintained.…”

“…Mathematically, the raw bit error rate (RBER) R0 for conventional flash can be estimated by, see e.g. [7],…”

Dynamic write-level and read-level signal design for MLC NAND flash memory

“…Previously the probability of error for flash memory is reported in [9], however it is based on simplified Gaussian channel. In this paper, we refer to channel model described in preceding section and compute the expression for probability of error.…”

“…Since the flash channel is non-stationary and varies over PE cycles, we would like to modify the verify-level voltages such that the overall probability of error is minimized. Until now, most of the research has been done on estimating the desired quantization-levels (read-level) based on the flash channel model [9], [11], [12], however, we propose to compute and adjust both verify-level (write-level) and quantization-level (read-level) voltage values according to channel condition. Given the channel parameters σ e and λ and mean threshold voltage of erased V min and highest programmed state V max which is device dependent parameter, we would like to optimize V 1 and V 2 by minimizing probability of error (4).…”

“…With similar approach we can modify (9) and optimize for any different quantization-levels. Using (8) and (9), we have plotted the capacity expression over different PE cycles with soft information (infinite-level) and PSO optimized 9-level, 15-level quantization for both proposed and fixed voltage schemes as shown in Fig.…”