Our proposed method L2D-CASKE, the lightweight 2-dimensional (2-D) Cellular Automata (CA) based symmetric key encryption algorithm is a 128 bit length that allows a key length of 128 bits. It is designed as a lightweight encryption algorithm. As being light weight, it can be easily applied on small devices such as wireless sensor motes, smart cards and other PDAs. An encryption algorithm having simple loop operations, based on iterative parameters is used in this work. A number of sequences and operations are used for this purpose. In this paper, the well designed algorithm was verified using MATLAB 7.7 (R2008) tool and the hardware synthesized on Field Programmable Gate Arrays (FPGAs). To achieve this, our algorithm uses loop design based on iterations and the same is realized on FPGA. Advantages of our algorithm can be listed in terms of its flexibility for a set of given constraints, less complexity involved in its performance. This is achieved through the usage of generic VHDL coding. Virtex-4 XC4VL25 -10ff668 is used as a test device in Xilinx 9.1 for realizing our algorithm.
SEA -Scalable Encryption Algorithm is a block cipher based symmetric encryption scheme, particularly intended for resource constrained devices. SEA proposes low computational cipher schemes, that is, miniaturized code size, memory and power, developed for processors with a restricted instruction set. SEA is parametric with plain-text, key and microprocessor size, and found to be powerful with the grouping of encipherment or decipherment and derivation of the keys. SEA was primarily meant for software implementations in microcontrollers, smart cards and small embedded systems. In this article, we look into the performance investigation of modified SEA with efficient modular adder in a Field programmable gate array (FPGA) device. For this reason, a loop based iterative design of the block cipher is realized on FPGA. Apart from its minimum cost, the proposed modified design is entirely flexible with any parameters and acquires advantage of generic VHDL coding. The efficient modular adders implementation based modification in SEA achieves lower area, power consumption and considerably higher throughputs on the target platform VIRTEX-4, xc4vl25 and SPARTAN-3, xc3s1400.
A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital filter is designed to implement a decimation factor of 64, operating at a maximum sampling frequency of 2.56 MHz. A second order sigma delta modulator is implemented in 0.18micron CMOS technology using full custom design and the third order digital CIC decimation filter is implemented in verilog HDL. The complete Sigma Delta ADC, consisting of analog block of second order modulator and digital block of decimator consumes a total power 1.96mW.
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