Implementation of Low Power Scalable Encryption Algorithm

Abstract

SEA -Scalable Encryption Algorithm is a block cipher based symmetric encryption scheme, particularly intended for resource constrained devices. SEA proposes low computational cipher schemes, that is, miniaturized code size, memory and power, developed for processors with a restricted instruction set. SEA is parametric with plain-text, key and microprocessor size, and found to be powerful with the grouping of encipherment or decipherment and derivation of the keys. SEA was primarily meant for software implementations in microcontrollers, smart cards and small embedded systems. In this article, we look into the performance investigation of modified SEA with efficient modular adder in a Field programmable gate array (FPGA) device. For this reason, a loop based iterative design of the block cipher is realized on FPGA. Apart from its minimum cost, the proposed modified design is entirely flexible with any parameters and acquires advantage of generic VHDL coding. The efficient modular adders implementation based modification in SEA achieves lower area, power consumption and considerably higher throughputs on the target platform VIRTEX-4, xc4vl25 and SPARTAN-3, xc3s1400.

Timestamp Based OTP and Enhanced RSA Key Exchange Scheme with SIT Encryption to Secure IoT Devices

“…Block ciphers have higher computational throughput, hence preferred the most. The Tiny encryption algorithm [19] is a block cipher algorithm, and it is one of the most efficient and straightforward algorithms used for data encryption. Moreover, the algorithm is designed following the memory constraints in IoT devices and have Shannon's properties of complete confusion and discussion by implementing substitution and permutation boxes.…”

Efficient Modular Adders for Scalable Encryption Algorithm

“…This is due to the fact that for a given processor, SEA uses a smaller sized ciphering routine and the security is achieved based on the key size. Since we operate on a limited resource processor, only some basic operations like XOR, AND, OR, efficient mod 2 b addition are done [3].…”

“…However, SEA"s efficient hardware implementation and performances are described by Standaert et.al [1,2] are yet to be investigated to meet efficiency in hardware costs. In [3], we proposed a modified SEA with a simple modular adder and successfully achieved efficiency in terms of area, power and Computation speed. This paper therefore further proposes to investigate this algorithm, modified for area and power in constrained applications, with different variants of modular adders.…”